You can go to the Editor, and type it in (or copy and paste it in), but this program is part of the collection of examples built in to Sigma16. Here's how to run it:

• Go to the Examples page. Click Examples, then Core, then Simple. This brings up a list of small and simple example programs. Click ConstArith.asm.txt. You should see the listing of the program. The file name has an extension .asm.txt that identifies the file as an assembly language source program.
• Click Editor, and you should see the text of the program in the window.
• Go to the Assembler page and click Assemble.
• Go to the Processor page. Click Boot, then Step repeatedly and watch the effect of each instruction by observing how the registers are changed.

The Processor page shows numbers in hexadecimal. The add instruction puts 14 into R10, and this is displayed as hex 000e.

It's a good idea to step through the program slowly, rather than running it to completion at full speed. The emulator will show the next instruction to be executed, highlighted in blue. Think about what the instruction should do; in particular what changes to the registers will occur? Then click Step and check to see if the right thing happened.

Generally you can use any register you like (apart from R0 and R15), and the choices of registers in the previous examples are arbitrary. Registers R1 through R14 behave the same. However, two of the registers are different:

• R0 contains the constant 0 and it will never change. Any time an instruction uses R0, the value it gets will be 0. It is legal for an instruction to attempt to modify R0 (for example, add R0,R3,R4 is legal) but after executing this instruction R0 still contains 0. The reason for this is that we frequently need to have access to a register containing 0.
• R15 is used for two specific purposes. We have already seen the first: the divide instruction places the remainder into R15. The second purpose is that R15 contains the condition code, which is a word that contains a number of bits that provide some information about an instruction. For example, if an addition produces a result that is too large to fit in a register, a special flag indicating this is set in R15. Several of the instructions, particularly the arithmetic instructions, change the value of R15 as well as placing the result in the destination register. For this reason, R15 cannot be used to hold a variable since its value would be destroyed almost immediately.

To summarise, Registers R1 through R14 are all identical and can be used for variables. R0 contains 0 and will never change. R15 changes frequently and can be used to detect various error conditions and other information about an instruction.

Here is another example:

• Suppose we have variables a, b, c, d
• And suppose we already have these variables in registers
• Choose a register for each variable: R1=a, R2=b, R3=c, R4=d
• We wish to compute R5 = (a+b) * (c-d)

     add   R6,R1,R2     ; R6 := a + b
     sub   R7,R3,R4     ; R7 := c - d
     mul   R5,R6,R7     ; R5 := (a+b) * (c-d)

Summary.

• A lea instruction of the form lea Rd,const[R0] will put the constant into Rd. It can also be written as lea Rd,const.
• The general form of an arithmetic instruction is op d,a,b. The meaning is R_d := R_a op R_b, and the fields are:
  • op is one of add, sub, mul, div
  • Rd is the destination register (where the result goes)
  • Ra is the register containing the first operand
  • Rb is the register containing the second operand

Since we need a lot of variables, they need to be kept in memory. But since we need to do arithmetic, and arithmetic can be performed only on data in registers, we adopt the following strategy:

• Keep variables permanently in memory.
• When you need to do arithmetic on some variables, copy them from memory to registers.
• When finished, copy the results from registers back to memory.

Two instructions are needed to do this:

• load copies a word from a memory location into a register. Suppose xyz is a variable in memory; then to copy its value into R2 we write load R2,xyz[R0].
• store copies a word from a register into a memory location. If R3 contains the result of some calculations, and we want to put it back into memory in a variable named result, we would write store R3,result[R0].

At this point we have enough instructions to write an assignment statement in assembly language. Typically we will first write an algorithm using higher level language notation, and then translate it into instructions. Translating from a high level language to assembly language is called "compiling".

Example: translate x := a+b+c into assembly language.

Solution:

    load   R1,a[R0]      ; R1 := a
    load   R2,b[R0]      ; R2 := b
    add    R3,R1,R2      ; R3 := a+b
    load   R4,c[R0]      ; R4 := c
    add    R5,R3,R4      ; R5 := (a+b) + c
    store  R5,x[R0]      ; x := a+b+c

The variables used in a program need to be defined and given an initial value. This is done with the data statement. The variable name comes first, and it must start at the beginning of the line (no space before it). Then comes the keyword data, followed by the initial value, which may be written in either decimal or hexadecimal. These pieces of the statement must be separated by white space.

For example, to define variables x, y, z and give them initial values:

x    data   34    ; x is a variable with initial value 34
y    data    9    ; y is initially 9
z    data    0    ; z is initially 0
abc  data  $02c6  ; specify initial value as hex

The data statements should come after all the instructions in the program. This may look surprising: in some programming languages you have to declare your variables at the beginning, before using them. There is a good reason why we will put the instructions first, and the data statements after; but the reason will come later.

Here is a simple example of a complete program that uses load, store, and data statements, to implement z := x + y.

; Program Add.  See README in top Sigma16 folder
; A minimal program that adds two integer variables

; Execution starts at location 0, where the first instruction will be
; placed when the program is executed.

      load   R1,x[R0]   ; R1 := x
      load   R2,y[R0]   ; R2 := y
      add    R3,R1,R2   ; R3 := x + y
      store  R3,z[R0]   ; z := x + y
      trap   R0,R0,R0   ; terminate

; Expected result: z = 37 (0025)

; Static variables are placed in memory after the program

x     data  23
y     data  14
z     data   0

Now you can run the program:

• Go to the Examples page. Click Core, then Simple, then Add.
• Click Editor, and you should see the text of the program in the window.
• Go to the Assembler page. Click Assemble.
• Go to the Processor page. Click Boot, then Step repeatedly and watch the effect of each instruction by observing how the registers and memory are changed.

The processor page shows the contents of the memory. For each memory location, the address is shown followed by the contents of that location. For example, if a line in the memory display shows 00b7 4c3f, this means that the memory location with address 00b7 contains 4c3f. This is written as M[00b7] = 4c3f.

Memory addresses and contents, as well as register contents, are shown in hexadecimal with no leading $. Since all these numbers are hexadecimal, putting $ in front (or 0x as in C) just adds distraction without telling you anything useful.

The processor displays two independent views into the memory. This is convenient because it's frequently necessary to look at two different portions of the memory at the same time. For example, it's helpful to look at the machine language code in one view and the data in the other view. With programs that use advanced techniques (e.g. pointers and activation records) it's essential to be able to view two different areas of memory. Despite the two views, there is just one memory.

The register file and the memory are similar in many ways, and they are also similar to ordinary arrays in some programming languages. The essential difference is that registers are fast but there are only a few of them, whereas memory is large but slow.

Why does the computer have both registers and memory? After all, this makes programming a little more complicated. You have to keep track of which variables are currently in registers, and you have to use load and store instructions to copy data between the registers and memory. Wouldn't it be easier just to get rid of the distinction between registers and memory, and do all the arithmetic on memory?

Yes, this would be simpler, and there have been real computers like that. However, this approach makes the computer slower. With modern circuits, a computer without load and store instructions (where you do arithmetic on memory locations) would run approximately 100 times slower. So nearly all modern computers do arithmetic in registers, and use instructions like load and store to copy data back and forth between registers and memory.

Every RRR instruction is represented in one word (16 bits), which is organised as four 4-bit fields. When describing a machine word, we normally write each field value as a hexadecimal digit: one of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f. These correspond to 0, 1, …, 15 in decimal.

The machine language code needs to specify which RRR instruction this is. Is it add? sub? mul? another? This is done with an operation code — a number that says what the operation is. There are about a dozen RRR instructions, so a 4-bit operation code suffices. For example, the add instruction has an opcode of 0.

We also need to specify three registers: destination and two source operands. There are 16 registers, so a specific one can be specified by 4 bits. Thus the requirements for an RRR instruction are 4 fields, each containing 4 bits, for a total of 16 bits, so an RRR instruction exactly fills one word.

The four fields in an RRR instruction are named:

• op – Operation code (e.g. add, sub, etc.) This is a number that specifies which instruction it is.
• d – Destination register
• a – First source operand register
• b – Second source operand register

Here are the operation codes for the RRR instructions we have seen so far. There are a few more RRR instructions, but they all have the same form as these do.

Don't memorise this table: you just need to understand how it's used. For example, let's translate this assembly language statement into machine language:

    mul  R14,R6,R10

1. mul is an RRR instruction, so we need to find the values of the four fields: op, d, a, b.
2. The table above says that the opcode for mul is $2 (that's 0010 as a bit string).
3. The destination is R14, so the d field is $e.
4. The first operand is R6, so the a field is $6.
5. The last operand is R10, so the b field is $a.
6. Putting the fields together ("assembling them into an instruction"), we get the machine language instruction: $2e6a.

Every RRR instruction is assembled the same way. The numbers in the fields will be different, but the procedure is always exactly the same.

We have seen several RX instructions so far:

    lea    R5,19[R0]   ; R5 = 19
    load   R1,x[R0]    ; R1 = x
    store  R3,z[R0]    ; z = R3

An RX instruction contains two operands, separated by a comma.

• The first operand is a register, and it's called the "register operand" (e.g. R5)
• The second operand is a constant or label followed by a register (e.g. 19[R0] or x[R0]). This is called the "address operand", and it contains two parts:
  • The first part is either a constant like 19, or a label like x. This part is called the "displacement", and its value is one word. If this part is a constant (e.g. 19) then the value of the displacement is simply the value of the constant. If it's a label like x, the value is the address in memory of x.
  • The seocnd part is a register in square brackets, e.g. [R0]. This is called the "index register". In the examples we've seen so far, the index register has always been R0, but in general it can be any register, and this is useful for several purposes we'll see later.

For RRR instructions, the op field contains a number saying which RRR instruction it is. This is the primary opcode. For RX instructions, the op field always contains f. So how does the machine know which RX instruction it is? This is specified by a secondary code in the b field. Here are the full codes (op and b) for a few of the RX instructions:

Consider this assembly language statement:

     lea   R2,38[R7]

There are two words in the machine language code. The first word has the same 4 fields as for RRR instructions: op, d, a, b, where

• op contains $f for every RX instruction
• d contains the register operand (in the example, $2)
• a contains the index register (in the example, $7)
• b contains a code indicating which RX instruction this is (1 means load). This "secondary opcode" is required because the op field just indicates that the instruction is RX format, but doesn't say which RX instruction it is.

The second word contains the displacement. In the example, this is 38 (or $0026).

If the address field of an instruction has a label (like x) rather than a constant (lik 204), we need to know the value of the label in order to assemble the instruction. If x is a variable, the value of the label x is the address of the variable in memory. If x is a label on an instruction, its value is the address of the instruction.

Example: translate load R7,x[R12] from assembly language to machine language, given that the address of x is $0c3a.

• First word:
  • op = $f (indicates that this is an RX instruction, but not which one; that needs the b field)
  • d = $7 (the register operand)
  • a = $c (part of the address operand: the register [R12])
  • b = $1 (this is the secondary opcode, which indicates that this RX instruction is load)
  • The first word is $f701
• Second word:
  • The displacement, part of the address operand, is $0c3a
• The complete machine language instruction: $f7c1 $0c3a

The instruction jump loop[R0] has only one operand in assembly language, which is loop[R0]. This looks like an exception: the other RX instructions have two operands. However, the machine language representation of jump also contains a register operand, just like all RX instructions, but the machine ignores that register when the program runs, and the assembler just sets it to R0 in the machine code. This is called a "don't care" operand.

We have seen conditional jump instructions like jumplt loop. Technically, jumplt, jumpeq and the rest are called "pseudoinstructions". They are just a convenient assembly language notations to describe the actual underlying machine language instructions. All conditional jumps are expressed in machine language using just two real instructions: jumpc0 and jumpc1:

    jumpc0 Rd,disp[Ra]
    jumpc1 Rd,disp[Ra]

The details of how jumpc0 and jumpc1 work will be discussed in the section on the Standard architecture. Here is a list of the pseudoinstructions for conditional jumps after an integer comparison:

    jumplt  someLabel[R0]  ; if <  then goto someLabel
    jumple  someLabel[R0]  ; if <= then goto someLabel
    jumpeq  someLabel[R0]  ; if =  then goto someLabel
    jumpne  someLabel[R0]  ; if != then goto someLabel
    jumpge  someLabel[R0]  ; if >= then goto someLabel
    jumpgt  someLabel[R0]  ; if >  then goto someLabel

Run the program with several different initial values of the variable y. These values are given below. For each run, assume that all the registers contain 0 after the program is booted, before it begins execution. For each value of y, do the following:

1. Edit the last statement of the program to give y the specified value.
2. Execute the program manually, with paper and pencil but without the computer. Give the final values of the registers. Think about what is going on as the program runs.
3. Assemble the program and boot it in the processor. Run the program on the emulator and check whether your execution was correct. Be sure to single-step through the program. Before executing an instruction, think about what it will do. Then click Step and look at the registers to see if you were right.

Here are the different variations:

1. Run the program in its original form, with y data 0
2. Change the last line to y data 1 and run it again
3. Now use y data 256
4. y data 8192
5. y data -5424

And here is the program:

; Strange: A Sigma16 program that is a bit strange    
        load   R1,y[R0]
        load   R2,x[R0]
        add    R2,R2,R1
        store  R2,x[R0]
        lea    R3,3[R0]
        lea    R4,4[R0]
x       add    R5,R3,R3
        add    R0,R0,R7
        trap   R0,R0,R0
y       data   0

It's best to try answering the questions on your own first, and then to check by running the program on the emulator, before reading the solution!

The program loads an instruction into a register, does arithmetic on it by adding y to it, and stores the result back into memory. This phenomenon is called self-modifying code, and it exploits the fact that instructions and data are held in the same memory (this is the stored program computer concept). The original instruction is add R5,R3,R3, and its machine language code is 0533.

1. When y=0, the final values are: R1=0, R2=0533, R3=3, R4=4, R5=6. The only notable points are that the store instruction doesn't actually change the value of the word in memory (it was 0533 and 0533 is being stored there), and the last add instruction doesn't change the value in R0 because R0 can never change; it is always 0. (Of course if R7=0 then the result of the addition is 0 anyway.)
2. When y=1, the final values are: R1=1, R2=0534, R3=3, R4=4, R5=7. Note that R5 is not 3+3=6. When y=1 is added to the instruction, the result is 0534 which means add R5,R3,R4, so instead of adding R3+R3 it adds R3+R4.
3. When y=256, the final values are: R1=256=0100, R2=0633, R3=3, R4=4, R5=0, R6=6. The decimal number 256 is 0100 in hexadecimal. When this is added to the instruction, the result is 0633, which means add R6,R3,R3 so R3+R3 is loaded into R6, not into R5.
4. When y=8192, the final values are: R1=4096=2000, R2=2533, R3=3, R4=4, R5=9. The decimal number 8192 is 2000 in hexadecimal, and when this is added to the instruction the result is 2533, which means mul R5,R3,R3. It's no longer an add instruction, it's a multiply instruction that calculates R5 := R3*R3 = 9.
5. When y=-5424 the program goes into an infinite loop. R1=ead0 (the hexadecimal representation of -5424), R2=f003, R3=3, and R4=4. What started out as the add instruction at x has been transformed into jump 7[R0], comprising the word at x (f003) and the following word (which is 0007). This jump instruction goes back to the first lea instruction, and the program runs for ever (lea, lea, jump).

There is a lot to say about the phenomenon of self-modifying code.

This program shows clearly that a computer does not execute assembly language; it executes machine language. Try running it on the Sigma16 application (single step each instruction). You'll see that the assembly language statement add R5,R3,R3 is highlighted in red, but that is just the GUI trying to be helpful. What's important is that the machine language instruction is fetched from memory and loaded into ir (the instruction register), and that is not 0533. The machine decodes the contents of ir and does whatever that says to do; it isn't aware of the assembly language statement. Indeed, a machine doesn't even understand the concept of assembly language — everything is just bits!

To follow exactly what is happening in the emulator, it's important to look at the pc and ir registers. These reflect what the machine is doing. The assembly language does not.

What is self-modifying code good for? The answer lies in the early history of electronic computers. Early computers (late 1940s and early 1950s) did not use an effective address (i.e. displacement + index) like Sigma16; the instructions simply specified the absolute memory address of an operand. This is ok for simple variables, but how could they process arrays?

The solution was to use self modifying code. In a loop that traverses an array, there would be a load instruction using address 0. In the body of the loop, there would be instructions to calculate the address of x[i] by loading the address of x and adding i; this is then stored into the address field of the load instruction. That instruction is then executed, obtaining the value of x[i]. This technique became obsolete in the early 1950s with the invention of index registers and effective addresses.

The pioneers of computers considered the concept of the stored program computer (i.e. the program and data are in the same memory) to be fundamental and essential. One of the most important reasons was that it made arrays possible. Now we consider the stored program concept to be fundamental for different reasons.

Self modifying code is tricky, and difficult to debug. It makes programs hard to read: you can't rely on what the program says, but on what its instructions will become in the future. For these reasons, self modifying code is now considered to be bad programming practice.

If a program modifies itself, you can't have one copy of the program in memory and allow it to be shared by several users. For example, it's common now to have a web browser open with several tabs. Each tab is served by an independent process (a separate running instance of a program that updates the window showing the web page). If you have 5 tabs open, there are 5 processes, each running the same machine language code, and there's only one copy of that in memory. This wouldn't work if the program modified itself!

Self modifying code leads to security holes: if a hacker has the ability to change your machine language code in memory, they could make your own program act against you.

Modern computers use a technique called segmentation that prevents a program from modifying itself. This leads to increased reliability and security.

Some computers have a facility that allows you to gain the power of self modifying code without actually modifying the code in memory. The idea is to have an instruction execute R1,x[R0] which calculates the logical or of the two operands and then executes the result; x is the address of an instruction and R1 contains the modification to it. The modified instruction is executed, but there is no change to the machine code in memory. This idea was used in the IBM 360 and its successors. However, as the design of effective addresses has become more sophisticated, the execute instruction is rarely needed, and most modern computers don't provide it.

A trap break is a trap instruction whose first operand register contains the value 4. The other operand registers are ignored. When this instruction is executed, the emulator will stop execution, and you can resume execution later by clicking Step or Run.

Suppose you want to check what the load instruction is doing in this code:

…
add    R1,R2,R3
load   R4,x[R1]
…

Insert a breakpoint just before the instruction you want to examine. The breakpoint requires two instructions. The first instruction loads the break code into some register (say R9 but it doesn't matter which), and the second instruction is a trap which performs the break. The first operand is the register that contains the break code, and the other two operands are ignored, so we can just use R0.

…
add    R1,R2,R3
lea    R9,4       ; R9 := trap break code
trap   R9,R0,R0   ; breakpoint
load   R4,x[R1]
…

Now you can run the program at full speed, but when it executes the trap instruction, the emulator will stop. Since the trap instruction has just executed, it will be highlighted in red, and the instruction you're interested in – the load – will be highlighted in blue. You can single step for a while, and click Run again at any time to resume full speed execution.

A common technique is to put a trap break at the beginning of a loop. By clicking Run repeatedly, you can step through the loop iterations.

For an example of a long running program with a trap break, see Examples / Core / Testing / Looper.

An external break tells the emulator to perform a breakpoint without modifying the program. Use these steps to set an external break:

1. Find the address of the instruction to stop at: look at the assembly listing, find the instruction, and the listing gives its address.
2. Go to the processor page, click Boot and then click Breakpoint.
3. A small window will appear; type in the breakpoint address. It must be a hexadecimal address in assembly language format: it must begin with a $ and then contain four hex digits. No other characters may be present, not even white space.
4. Click Refresh. This parses the address you entered and remembers it. (If you change the address in the window, click Refresh again.)
5. Click Enable. This turns on the breakpoint.
6. Click CLose. The breakpoint popup window will disappear so you can see the Processor again.

Now click Run and the program will execute at full speed. When the pc register is equal to the breakpoint address, the emulator will stop. Then you can Step or Run to continue execution.

As long as the breakpoint is enabled, execution will stop every time that location is encountered. To prevent this, open the breakpoint popup again and click Disable.

It isn't required to have a semicolon ; before every comment. If an assembly language statement has an operation field and an operand field, then everything after the operand field is taken to be a comment.

     lea  R3,42[R0]    This is a comment
     load R5,xyz[R0]   ; and so is this

Although most assembly language statements have an operand field, some do not. In these cases, the semicolon is required to indicate a comment.

It's good style to use a semicolon consistently to indicate a comment, even where it wouldn't be required.

The instruction lea R3,42 is an abbreviation for the complete form, lea R3,42[R0]. In an RX instruction, if you omit the [Reg] after the displacement, the assembler will automatically use [R0]. The following two assembly language statements describe the same instruction:

     lea  R3,42[R0]   ; R3 := 42
     lea  R3,42       ; R3 := 42

You can write the instruction either way; both are translated to exactly the same machine language, and they execute exactly the same way. These are also equivalent:

     jumplt loop[R0]  ; if < then goto loop
     jumplt loop      ; if < then goto loop

Word logic operations are "bitwise": bit \(i\) of the result depends on bit \(i\) of each operand, and does not depend on bits at any other index. There are pseudoinstructions for the most common word logic operations: invw, andw, orw, xorw.

The invw pseudoinstruction inverts all the bits in a register:

lea   R3,$f0f0[R0]   ; R3 := f0f0
invw  R3             ; R3 := 0f0f

The other word logic pseudoinstructions take two register operands. They calculate the result and place the result in the first operand register, overwriting its previous value. There is not a separate destination register, as in the add instruction.

For example, andw R1,R2 calculates the logical and of R1 and R2, and places the result in the destination register R1.

lea   R1,$f0f0[R0]   ; R1 := f0f0
lea   R2,$00ff[R0]   ; R2 := 00ff
andw  R1,R2          ; R1 := 00f0

The orw (logical inclusive or) and xorw (logical exclusive or) instructions are similar.

lea   R1,$f0f0[R0]   ; R1 := f0f0
lea   R2,$00ff[R0]   ; R2 := 00ff
orw   R1,R2          ; R1 := f0ff
xorw  R1,R2          ; R1 := f000

There are also pseudoinstructions that perform logic on two individual bits, which may be at any index in any register. The result overwrites the first operand. For example, andb R1,R2,3,9 calculates R1.3 and R2.9 and stores the result in R1.3. Here are some examples:

   lea     R1,$00ff[R0]   ; R1 := 00ff
   lea     R2,$00f0[R0]   ; R2 := 00f0
   andb  R1,R2,3,9        ; R1 := 00f7
;       (R1.3 := R1.3 and R2.9 = 1 and 0 = 0)
   orb  R1,R2,11,5        ; R1 := 08f7
;       (R1.11 := R1.11 or R2.5 = 0 or 1 = 1)
   xorb  R1,R2,4,6        ; R1 := 08e7
;       (R1.4 := R1.4 xor R2.6 = 1 xor 1 = 0)

You can set an individual bit in a register at a specified index to 0 using clearb. The first operand is a register, and the second operand is the index of the bit. All other bits in the register remain unchanged. So clearb R3,2 makes R3.2 zero (that is, the bit at index 2 in R3). All the other bits in R3 remain unchanged.

lea     R3,$ffff[R0]  ; R3 := ffff
clearb  R3,2          ; R3 := fffb  (R3.2 := 0)

setb is similar, but it makes the specified bit 1.

lea     R3,$ffff[R0]  ; R3 := ffff
clearb  R3,2          ; R3 := fffb  (R3.2 := 0)
add     R4,R0,R0      ; R4 := 0000
setb    R4,6          ; R4 := 0040  (R4.6 := 1)

There are two shift instructions, which shift the word in Re by f bits (to left or right) and place the result into Rd. These are logical shifts: the bits that are shifted out are discarded, and bits shifted into the word are always 0.

shiftl Rd,Re,f  ; Rd := Re shifted left by f bits
shiftr Rd,Re,f  ; Rd := Re shifted right by f bits

Here are some examples; the comments show the expected result in both hexadecimal and as bits.

lea    R1,2[R0]  ; R2 = 0002   0000 0000 0000 0010
shiftl R5,R1,4   ; R5 = 0020   0000 0000 0010 0000
shiftl R6,R1,13  ; R6 = 4000   0100 0000 0000 0000
shiftr R7,R6,3   ; R7 = 0800   0000 1000 0000 0000
shiftr R7,R7,11  ; R7 = 0001   0000 0000 0000 0001

A common situation, especially in systems programming, is that you have a word that contains several fields. A machine language instruction is like that; also a network packet contains a number of fields. The sizes of the fields, and their positions within a word, can be anything. Software, especially systems programming, often needs to be able to extract a field from a word and put it somwhere else so it can be used.

It's possible to obtain any field from a register, and put it somewhere in another register, using a sequence of shift and logic instructions (particularly shiftl, shiftr, andw, orw). However, these sequences of instructions are error prone, hard to read, and they execute frequently in the inner loop of many systems programs.

Sigma16 provides an instruction extract which solves this problem with just one instruction. It allows you to extract an arbitrary field from a register and put it into an arbitrary location in another register.

The extract instruction takes operands that specify the source register (which contains the field you're interested in), the destination register (where it will put the field), the location of the field in the source register (specifed as the index of the rightmost and leftmost bits in the field), and the location where you want to put the field in the destination register.

This instruction copies 4 bits from R1.4:7 to R2:8:11:

extract  R2,R1,8,4,7   ; R2.8:11 := R1.4:7

In this example, the operands are:

• R2 is the destination register
• R1 is the source register
• 8 is the index of the rightmost bit in the destination where the field will be placed at ascending bit indices
• 4 is the index of the rightmost bit of the field in the source register
• 7 is the index of the leftmost bit of the field in the source register

This instruction is equivalent to the following (although it is just one instruction, not four instructions):

R2.8  :=  R1.4
R2.9  :=  R1.5
R2.10 :=  R1.6
R2.11 :=  R1.7 

The extract instruction modifies only the specified bits in the destination register; the other bits remain unchanged.

Here is an executable example:

lea      R1,$00f0[R0]  ; R1 = 00f0
add      R2,R0,R0      ; R2 = 0000   
extract  R2,R1,8,4,7   ; R2 = 0f00  R2.8:11 := R1.4:7

The bits of a word are indexed from right to left, starting with index 0. The least significant (rightmost) bit has index 0, and the most significant bit (leftmost) has index 15.

The notations \(x_i\) and x.i both mean the bit with index \(i\) in the word \(x\), for \(0 \leq i \leq 15\). For example, \(x_0\) is the rightmost bit and \(x_{15}\) is the leftmost bit. When used in an instruction, a bit index is specified as a 4-bit binary number \(i\) such that \(0 \leq i \leq 15\).

The following table shows the indices of all the bits in a word. The vertical bars break the word into groups of 4 bits. This grouping corresponds to the representation of the word in hex notation.

\[\fbox{$\ x_{15}\> x_{14}\> x_{13}\> x_{12} \ \vert\ x_{11}\> x_{10}\> x_{9}\> x_{8}$}\]

\[\fbox{$ \ \vert\ x_{7}\> x_{6}\> x_{5}\> x_{4} \ \vert\ x_{3}\> x_{2}\> x_{1}\> x_{0} \ $}\]

A bit field is a contiguous sequence of bits in a word. It is specified by two numbers: the indices of the rightmost and leftmost bits in the field.

The natural numbers are \(0, 1, 2, \ldots\), so all natural numbers are nonnegative. Sigma16 represents natural numbers as binary, and uses them to represent memory addresses. The binary value of an \(n\) bit generic word \(x\) is

\[binval (x) = \sum_{0 \leq i < n} x_i * 2^i\]

For a word of 16 bits, natural numbers are restricted to the range from 0 through \(2^{16}-1\); that is, from 0 through 65,535. For a double word (32 bits), natural numbers are restricted to the range from 0 through \(2^{32}-1\); that is, from 0 through 4,294,967,295.

A natural number (and hence a binary number) cannot be negative. If you need numbers that can be negative or positive, you must use an integer. The arithmetic instructions in Sigma16 operate on integers, but address arithmetic is performed in binary.

Integers are represented using two's complement notation. If the leftmost (most significant) bit of a word is 0, its two's complement value is the same as its binary value. If the leftmost bit is 1, the two's complement value is negative.

Any two's complement number (with one exception) can be negated by inverting all the bits (replace 0 by 1 and vice versa) and then adding 1, discarding any overflow. The sole exception is that if the smallest negative number (\(-2^{15}\)) is negated, the result is overflow because the largest positive integer representable in 16 bit two's complement is \(2^{15}-1\).

For example, consider \(x\) = 1111 1010. Since the leftmost bit is 1, we know that \(x < 0\). We can negate \(x\) by inverting the bits, obtaining 0000 0101. Adding 1 gives 0000 0110 which is 6. Since \(-x = 6\), we conclude that \(x = -6\).

Assembly language provides several notations for expressing the value of a word.

• A natural number between 0 and 65,535 (2¹⁶ - 1)
• An integer between -32,768 and 32,767 (-2¹⁵ and 2¹⁵ - 1)
• A 4-digit hexadecimal constant, where the digits are 0-9 a-f. The constant is preceded by $, for example $3e8c.

In assembly language programs, hexadecimal constants are written with a preceding $ sign (e.g. $3b2f). This is necessary to avoid ambiguity: 1234 is a decimal number and $1234 is a hexadecimal number, and they denote different words.

Assembly language always requires a $ before a hexadecimal constant. For displays of the machine state, in contexts where there is no ambiguity, the $ may be omitted. For example, the user interface displays register and memory contents as hexadecimal without the leading $. However, the $ is always required for hex constants in assembly language programs.

The register file is a set of 16 general registers, each of which holds a 16 bit word. A register is referenced by a 4-bit binary number. In assembly language, we use the notations R0, R1, R2, …, R9, R10, R11, R12, R13, R14, R15 to refer to the registers. The state of the register file can be written as a table showing the value of each register:

Sigma16 is a load/store style architecture. All calculations are carried out in the register file, and explicit load and store instructions must be used to copy data between the memory and the register file.

R0 and R15 are special. The other registers, R1 through R14, may be used for any purpose.

• R0 always contains the constant 0.

It is legal to perform an instruction that attempts to load some other value into R0, but the register will still contain 0 after executing such an instruction. Such an instruction will simply have no lasting effect.

• R15 is the condition code register.

Several instructions produce status information: the result of a comparison, whether there was an overflow, etc. This information is automatically loaded into R15, which is also called the condition code. The description of each instruction states whether R15 is modified, and what goes into it.

Each bit in the condition code (R15) is a Boolean that specifies whether a specific condition is false (0) or true (1). The bits are indexed from bit 0 (rightmost, or least significant) to bit 15 (the leftmost, or most significant). Condition code bits are sometimes called flags. Each flag gives the status of a relation or event. If the flag is True (1) the relation holds or the event has occurred. If the flag is False (0) the relation does not hold, or the event has not occurred.

One way to use flags in the condition code is to control conditional jumps. The jumpc0 and jumpc1 instructions are conditional jumps that use a flag in R15 to decide whether to jump:

• Use jumpc0 to jump if the Boolean is False
• Use jumpc1 to jump if the Boolean is True

Both jumpc0 and jumpc1 take two operands. The first is a natural number from 0 to 15, which gives the index of a flag in the condition code. The second is an address to jump to, specified as displacement[index]. The indices of the flags are given below.

The two conditional jumps (jumpc0 and jumpc1) let you jump depending on either the truth or falsity of a condition. For example, the flag at index 4 denotes integer less than. The fist pair of instructions below jumps if the less than condition holds, and the second pair jumps if the less than condition is false. This is equivalent to jumping if the "greater than or equal" condition holds.

cmp     R8,R9
jumpc1  4,xyz[R0] ; if R8 < R9 then goto xyz
…
cmp     R8,R9
jumpc0  4,xyz[R0] ; if R8 >= R9 then goto xyz

Programs usually use pseudoinstructions rather than the actual machine instructions jumpc0 and jumpc1. For example, the following two instructions are equivalent: the assembler generates exactly the same machine language code for them.

jumpc1  4,xyz[R0] ; if R8 < R9 then goto xyz
jumplt  xyz[R0]   ; if R8 < R9 then goto xyz

In effect, the pseudoinstruction lets you omit the flag index and instead to indicate the condition you want in the mnemonic. It's easier to remember that less than is indicated by lt than by 4.

Another way to use condition code flags is to save them as Boolean variables and perform logic operations on them. In this case it's best to copy a flag to another register, using copyb. From there you can evaluate logic expressions using andb, orb, xorb, and logicb. It isn't a good idea to keep Boolean variables in R15 for a long time, because many instructions will modify it.

Before doing logic operations on condition code bits, consider whether "short circuit" evaluation, with a separate comparison followed by conditional jump for each relation, is more appropriate.

There is not just one flag for "less than" and another for "greater than". There are separate flags for integers (represented as two's complement) and natural numbers (represented as binary). This is necessary because the relation between two words sometimes depends on the type of the data. For example, consider the word ffff (all 1 bits). On its own, ffff is just a word of bits and has no inherent meaning.

• If ffff is interpreted as a natural number (i.e. binary), it is positive and has the value 65,535, and ffff > 0000.
• If ffff is interpreted as an integer (i.e. two's complement), then it is negative and has the value -1, and ffff < 0000.

The cmp instruction compares two words, and evaluates five relations between the words: equality, less than for both natural and integer, and greater than for both natural and integer. These evaluations are performed simultaneously, using parallelism in the ALU circuit, and the result of each is recorded in the corresponding flag in the condition code.

    cmp    R5,R6
    jumpc1 3,lessNat[R0]  ; if R5 <Nat R6 then goto lessNat
    …
    cmp    R7,R8
    jumpc1 4,LessInt[R0]  ; if R7 <Int R8 then goto lessInt

Thus you don't specify the types of the operands in the cmp instruction. Instead, you select the condition code flag that corresponds to the types.

Each flag has a short 1-character name to enable it to be displayed compactly in the user interface. A naming convention is that flags for integers (two's complement) have lower case letters, while flags for natural numbers (binary) have upper case letters. For example:

• l means < for integers
• L means < for natural numbers
• g means > for integers
• G means > for natural numbers

Equality is the same regardless of type. If two words consist of exactly the same bits, then they have the same value as integers, natural numbers, characters, addresses, and for any other possible type as well. Therefore there is only one flag for equality, and its symbol is =.

Register R15 is also called the condition code. Some instructions modify a bit in the condition code to indicate the results of comparisons, overflow, carry, other special data, and various errors. Instructions that operate on registers can access R15 as usual. There are also some instructions that implicitly access R15 without specifying it (for example, jumpc0 and jumpc1). Since many instructions modify the condition code as a side effect, programs should not use R15 to hold variables.

The following table lists all the condition code flags.

• Index is the bit position of the flag in the condition code. Bits are numbered from right to left, starting with 0.
• Symbol: the graphical user interface shows the symbol for each bit that is 1. For example, if G is displayed after a comparison of two words, this means that > holds if the words are interpreted as natural numbers but not if they are interpreted as integers. However, if G> is displayed, the comparison result is greater than for both integer and two's complement representation.
• Meaning: Description using English or mathematical notation
• Hex: The value of the condition code word assuming the given flag is true and all others are false. If several flags are true, the condition code register will be the logic or of the hex values of the true flags. For example, suppose the words 00a3 is compared with 00c5. The comparison result is L (less than for naturals) and also l (less than for integers). So the condition code will contain 0008 + 0010 = 0018.

Table: Condition code flags

There is an exception for division by zero, but no corresponding flag in the condition code. The reason is that the div instruction places the remainder in R15, so the condition code isn't available to represent division by 0. You can use an interrupt to detect division by 0, and you can test explicity for division by 0 by using jumpz specifying the register containing the divisor before executing the div instruction.

The instruction control registers enable the processor to keep track of the state of the running program. These registers are rarely used directly by the machine language program, but they are essential for keeping track of the execution of the program, and some instructions use them directly.

The mask register specifies which types of interrupt are allowed to occur. It contains a flag for each type of interrupt; if the flag is 1 then the corresponding type of interrupt can take place. If the mask flag is 0, then that type of interrupt will not occur even if it is requested.

When an interrupt is requested, the corresponding bit is set in the request register. When the next instruction is executed, the interrupt occurs if interrupts are enabled and the corresponding mask bit is 1.

When an interrupt occurs, the value of the status register is copied into rstat.

When an interrupt occurs, the value of pc is copied into rpc. This is necessary to enable the operating system to resume the interrupted program.

The interrupt vector register contains the address of a jump table. This is an array of jumps to interrupt handlers.

The RRR format is used for instructions that perform calculations in the registers, without using memory.

An instruction in RRR format is one word containing four 4-bit fields called op, d, a, b. Each field contains 4 bits representing a binary number between 0 and 15.

• op (bits with index 15 to 12) is the operation code, usually called opcode. This determines the operation to be performed. If the opcode is between 0 and 12 it specifies an RRR instruction. An opcode greater than 12 indicates an expanding opcode: the instruction is not RRR but one of the other formats, and it has a secondary opcode that specifies precisely which instruction it is. This is explained in the sections on RX and EXP formats.
• d (bits 11 to 8) is the destination register; the register where (in most cases) the result will be loaded.
• a (bits 7 to 4) is the register containing the first operand.
• b (bits 3 to 0) is the register containing the second operand.

In most cases, an RRR instruction takes two operands in registers specified by the a and b fields and produces a result which is loaded into the register specified by the d field.

A typical example of an RRR instruction is add R4,R13,R2, which adds the contents of registers R13 and R2, and loads the result into R4. It's equivalent to R4 := R13 + R2. The opcode for add is 0, so the machine language code for this instruction is 04d2.

The RX format is used for instructions that use a memory location. There are generally two operands: one is a register and the other is a word in memory.

RX instructions specify a memory location as well as a register operand. The machine language representation is two words:

Here is RX

The RX instruction format is used for instructions that use a memory address, which is specified by an index register and a displacement. The name of the format describes briefly the two operands: a register (R) and an indexed memory address (X).

An RX instruction contains two operands: one is a memory address, and the other is a register. Typical RX instructions are loads, stores, and jumps. The instruction consists of two consecutive words. The first has the same format as an RRR instruction, with four fields: op, d, sa, sb. The second word is a single 16-bit binary number, and is called the displacement.

An RX instruction is represented by two words, with the following fields: op=15, b contains the secondary opcode which specifies which RX instruction it is, d is the destination, a is the index register, and the second word is a 16 bit constant called the displacement (often written disp for short).

• op field (bits 0-3 of ir) is f for all RX instructions
• d field (bits 4-7 of ir) has several uses
• a field (bits 8-11 of ir) is index register for effective address
• b field (bits 12-15 of ir) is secondary opcode
• disp (displacement) is the second word of the instruction
• ea (effective address) = displacement + r[a]

The memory address is specified in two parts: an index register and the displacement. The index register is specified in the sa field. In assembly language, the notation used is number[reg], where the number is the value of the displacement, and the reg is the index register. Thus $20b3[R2] means the address has displacement $20b3 and the index register is R2.

When the machine executes an RX instruction, it begins by calculating the effective address. This is abbreviated "ea", and its value is the sum of the displacement and the contents of the index register.

RX instructions are represented in two words, and they use an "expanding opcode". That is, the op field of the first word of the instruction contains the constant f (the bits 1111) for every RX instruction, and the sb field is used to hold a secondary opcode indicating which RX instruction it is.

The register operand is specified in the d field. For several RX instructions, this is indeed the destination of the instruction: for example, load places data into Rd. However, a few RX instructions use the d field differently (see, for example, the conditional jump instructions).

The memory address is specified using the sa field and the displacement, which is the entire second word of the instruction.

The RX format is used for instructions that access the memory. There are two operands: a memory address and a register. The memory address is specified using two fields: a constant (called the displacement) and a register (called the index register).

An RX instruction consists of two words. The first has the same format as RRR. The op field is 15, which means "this instruction has RX format". A secondary operation code is needed to specify which RX instruction this is, this is given in the b field. The d field is the destination register, and the a field is the index register. There is only one operand register for RX instructions, since the b field is needed for the secondary operation code.

The second word consists of one 16-bit field called the displacement (abbreviated as disp).

The index register Rb and the displacement together specify the effective address. The assembly language syntax for the effective address is disp[Rb], and its value is \(\mathrm{disp} + \mathrm{Rb}\). For example, suppose R4 contains 7 when the following instruction is executed:

load  R2,5[R4]

The address operand is 5[R4], where the displacement is 5 and the index is R4. When the instruction executes, the effective address is \(5 + \mathrm{R4} = 5 + 7 = 12\), or $000c.

The displacement is a constant given in the instruction, but the index register is variable. Since R0 always contains 0, the effective address for disp[R0] is the value of disp.

The displacement is represented in binary, and the effective address is calculated in binary, not in two's complement. Thus the effective address of ffff[R0] is the (positive) address of the last word in memory – it isn't a negative number.

The EXP instructions provide more complex operations, and they belong to the Standard architecture. (The Core architecture uses only RRR and RX). An EXP instruction consists of two words.

The first word has the same op and d fields as RRR and RX. The op field contains 14 (hex e), which indicates that the instruction is EXP format. The a and b fields are treated as one 8-bit natural number, which is the secondary operation code. This provides for the possibility of up to 256 EXP format instructions, which enables new experimental instructions to be defined.

The second word contains for 4-bit fields. Each of these may contain either a register number or a short 4-bit number, depending on the instruction.

We usually write instructions in assembly language (sub R3,R12,R9) but the computer executes machine language (13c9). There is a precise relationship between these two notations for an instruction. By writing assembly language, you determine the exact value of every bit in every word of a machine language program. This section explains how these two notations for an instruction are related.

When each instruction is described below, an example is given showing a typical use of the instruction, along with the general form of the assembly language instruction.

The general form uses the machine language field names to show where each piece of the instruction goes in the machine code. The instruction format is also given, along with any constant fields.

As an example, the logicu instruction is EXP format, so its machine language representation consists of two words with the following fields:

The primary opcode is e, which goes in the op field. The secondary opcode is 14, which goes in the ab field. Thus op=e, a=1, and b=4 (here, a dollar sign is used before the hex constants to distinguish them from the field names).

and the For example, here is the general form of the logicu instruction:

logicu  Rd,e,Rf,g,h     ; Rd.e := h (Rd.e, Rf.g)
EXP op=#e ab=$14

logicu  Rd,e,Rf,g,h     ; Rd.e := h (Rd.e, Rf.g)
EXP op=#e ab=$14

The format is EXP, so the instruction has all the fields of the EXP format: op, d, ab, e, f, g, h. There are two constant fields: the primary opcode (op) is $e, and the secondary opcode (ab) is $14. The values of the other fields are given in the general form of the assembly language. The operands Rd and Rf refer to registers, and those register numbers go into the d and f fields of the instruction. The e, g, and h fields are given as numbers in the assembly language. (The assembly language convention is to give constants in decimal notation, not hexadecimal.)

Example:

logicu  R7,5,R2,13,xor ; R7.5 := R7.5 xor R2.13
e714 52d6

The instruction add Rd,Ra,Rb has operands Ra and Rb and destination Rd. It fetches the operands Ra and Rb, calculates the sum Ra + Rb, and loads the result into the destination Rd. The effect is Rd := Ra + Rb. For example, add R5,R12,R2 performs R5 := R12 + R3.

As well as setting the destination register, the add instruction sets or clears the overflow and carry bits in the condition code (which is R15). The other bits in R15 are not changed.

If the destination register is R15, the sum is placed in R15, and the overflow and carry flags are discarded.

The add instruction is RRR format with opcode=0. Given destination Rd and operands Ra and Rb (where d, a, b are hex digits), add Rd,Ra,Rb is reprseented by 0dab.

Examples:

A field is a consecutiave sequence of bits within a word. A field is specified with the index of the leftmost bit in the field, along with the size of the field. For example, the field in x with index 9 and size 3 consists of the bits x.9 x.8 x.7.

add R1,R2,R3    ; R1 := R2 + R3

The instruction add Rd,Ra,Rb has operands Ra and Rb and destination Rd. It fetches the operands Ra and Rb, calculates the sum Ra + Rb, and loads the result into the destination Rd. The effect is Rd := Ra + Rb. For example, add R5,R12,R2 performs R5 := R12 + R3.

The add instruction is RRR format with opcode=0. Given destination Rd and operands Ra and Rb (where d, a, b are hex digits), add Rd,Ra,Rb is reprseented by 0dab.

The add instruction can be used for both binary addition (on natural numbers) and for two's complement addition (on signed integers).

• 16-bit natural numbers are unsigned integers 0, 1, 2, …, 65535. If two natural numbers are added, the result is a natural number (the result cannot be negative). If the result is 65536 or larger, it cannot be represented as a 16 bit binary number. If this happens, the destination register is set to the lower 16 bits of the true result, and the binary overflow flag is set in the Condition Code.
• 16-bit two's complement numbers are signed integers -32999?, …, -1, 0, 1, …, 32???. If two signed integers are added, the result is a signed integer. If the result is less than -32000 or greater than 32000, then the result cannot be represented as a 16 bit two's complement number. If this happens, the destination register is set to the lower 16 bits of the true result, and the two's complement overflow flag is set in the Condition Code. Furthermore, the overflow flag is set in the req register. If interrupts are enabled and the overflow flag is 1 in the mask register, then an interrupt will occur immediatelhy after the add instruction executes.

The add instruction can be used for both binary addition (on natural numbers) and for two's complement addition (on signed integers).

• 16-bit natural numbers are unsigned integers 0, 1, 2, …, 65535. If two natural numbers are added, the result is a natural number (the result cannot be negative). If the result is 65536 or larger, it cannot be represented as a 16 bit binary number. If this happens, the destination register is set to the lower 16 bits of the true result, and the binary overflow flag is set in the Condition Code.
• 16-bit two's complement numbers are signed integers -32999?, …, -1, 0, 1, …, 32???. If two signed integers are added, the result is a signed integer. If the result is less than -32000 or greater than 32000, then the result cannot be represented as a 16 bit two's complement number. If this happens, the destination register is set to the lower 16 bits of the true result, and the two's complement overflow flag is set in the Condition Code. Furthermore, the overflow flag is set in the req register. If interrupts are enabled and the overflow flag is 1 in the mask register, then an interrupt will occur immediatelhy after the add instruction executes.

Example: sub R1,R2,R3 ; R1 := R2 - R3

This instruction is similar to add; the only difference is that it calculates R2-R3 and places the result in R1. The effect on the condition code is the same as for add.

The instruction sub Rd,Ra,Rb has operands Ra and Rb and destination Rd. It fetches the operands Ra and Rb, calculates the difference Ra - Rb, and loads the result into the destination Rd. The effect is Rd := Ra - Rb. For example, sub R5,R12,R2 performs R5 := R12 - R3.

The sub instruction is RRR format with opcode=1.

In addition to setting the destination register, the sub instruction sets several bits in the condition code R15 and may set a bit in the req register.

Example: mul R1,R2,R3 ; R1 := R2 * R3

The multiply instruction mul Rd,Ra,Rb calculates the integer (two's complement) product of the operands Ra and Rb, and places the result in the destination register Rd. The mul instruction does not produce the natural (binary) product.

If the magnitude of the product is too large to be representable as a 16 bit two's complement integer, this is an overflow. If overflow occurs, the integer overflow bit is set in the condition code (F15) and the integer overflow bit is also set in the interrupt request register (req), and the lower order 16 bits of the product are loaded into Rd.

Example: div R1,R2,R3 ; R1 := R2 / R3, R15 := R2 rem R3

Unlike the other arithmetic operations, the divide instruction div Rd,Ra,Rb produces two results: the quotient Ra / Rb and the remainder Ra rem Rb. It loads the quotient into the destination register Rd, and the remainder is loaded into R15.

If the destination register Rd is R15, then the quotient is placed in R15, and the remainder is discarded.

The divide instruction doesn't set the condition code, since R15 is used for the remainder. Therefore there is no condition code bit to indicate division by 0. However, it is easy for a program to detect a division by 0.

• (Explicit test for error) The program can compare the divisor with 0 before or after executing the divide instruction, and jump to an error handler if the divisor is 0. This is similar to testing the condition code after an add, sub, or mul instruction, but it does require two instructions: a compare followed by a conditional jump. For example:

div    R1,R2,R3       ; R1 := R2/R3, R15 := R2 rem R3
cmp    R3,R0       ; Did we divide by 0?
jumpeq zeroDivide[R0] ; If yes, handle error

• (Exception) The program can detect division by 0 using an interrupt. To do this, enable interrupts and enable the interrupt mask for division by 0. See the section on Interrupts. This approach does not require a compare or jump instruction for each division.

The compare instruction cmp Ra,Rb compares the values in the operand registers Ra and Rb, and then sets flags in the condition code (R15) to indicate the result. The notation R15.i means bit i in R15; thus R15.0 is the leftmost bit of R15. The instruction performs both natural number comparison (binary) and integer comparison (two's complement). The resulting flags are

• binary less than (L) in R15.0
• two's complement less than (<) in R15.1
• equal in R15.2
• binary greater than (G) in R15.3
• two's complement greater than (>) in R15.4

The result of a cmp instruction can be used to control a conditional jump. The jumpc0 instruction jumps is a specified bit of R15 is 0, and the jumpc1 instruction jumps if a specified bit is 1.

Pseudoinstructions provide the most common cases; for example jumple jumps if the condition code indicates that a comparison produced either integer less-than or equal. A common pattern is a cmp followed by a jump pseudoinstruction, for example:

cmp     R4,R9      ; compare R4 with R9
jumpgt  abc]R0]    ; if R4 > R9 then goto abc

The addc instruction performs a binary addition with carry propagation. It adds the two operand registers and the carry bit in the condition code register, R15. The sum is loaded into the destination register Rd and the carry output is written back into the carry bit, overwriting its previous value. Overflow is not possible with this instruction.

muln   Rd,Ra,Rb

The muln instruction calculates the product of two natural numbers in Ra and Rb. The result is 32 bits; the leftmost 16 bits (the most significant part) is loaded into R15, and the rightmost 16 bits (the least significant part) is loaded into Rd. If Rd is R15, the most significant part is discarded.

divn   Rd,Ra,Rb

The divn instruction divides two natural numbers: dividend / divisor. All the numbers – numerator, denominator, quotient, remainder – are natural numbers represented in binary.

• The dividend is a 32 bit natural number; its leftmost 16 bits are in R15 and the rightmost 16 bits are in Ra. Thedenominator is in Rb.
• Two results are produced: a 32-bit quotient anda 16-bit remainder.
• The leftmost 16 bits of the quotient are placedin R15 (replacing the leftmost part of the dividend). The rightmost16 bits of the quotient are placed in Rd.
• The remainder is placed in Ra, overwriting the least significant half of the dividend operand

The load effective address instruction lea Rd,disp[Ra] calculates the effective address of the operand disp[Ra] and places the result in the destination register Rd. The effective address is the binary sum disp+Ra.

The load instruction load Rd,disp[Rx] calculates the effective address of the operand disp[Rx] and copies the word in memory at the effective address into the destination register Rd. The effective address is the binary sum disp+Rx.

Examples

load  R12,count[R0]   ; R12 := count
load  R6,arrayX[R2]   ; R6 := arrayX[R2]
load  R3,$2b8e[R5]    ; R3 := mem[2b8e+R5]

The store instruction store Rd,disp[Rx] calculates the effective address of the operand disp[Rx]. The value of the destination register Rd is stored into memory at the effective address.

Store copies the word in the destination register into memory at the effective address. This instruction is unusual in that it treats the "destination register" as the source of data, and the actual destination which is modified is the memory location.

Most instructions take data from the rightmost operands and modify the leftmost destination, just like an assignment statement (x := y+z). However, the store instruction operates in the opposite direction. The reason for this has to do with the circuit design of the processor. Although the "left to right" nature of the store instruction may look inconsistent from the programmer's point of view, it actually is more consistent from the deeper perspective of circuit design.

Examples

store  R3,$2b8e[R5]
store  R12,count[R0]
store  R6,arrayX[R2]

Three instructions (push, pop, top) support operations on a stack represented as an array of contiguous elements, where the stack grows from lower to higher addresses. These instructions provide safe operations: they never overwrite memory outside the stack, and they indicate stack underflow and overflow by setting the condition code and optionaly performing an exception.

A stack is represented by three addresses, which are provided to the push, pop, and top instructions in registers:

• The stack base is the address of the first word allocated for the stack.
• The stack limit is the address of the last word allocated for the stack.
• The stack top is the address of the stack element that was pushed most recently.

Although three addresses are required to characterise the state of a stack, each individual stack instruction (push, pop, top) requires only two of those addresses. These are supplied as the Ra and Rb operands, while Rd is used to supply or receive the data value.

The maximum number of elements the stack may contain is stack limit - stack base + 1. Normally, stack limit is greater than stack base. If they are equal, there is only one word allocated for the stack (which is generally not useful), and if stack base > stack limit then no memory at all is allocated and every stack operation will signal an underflow or overflow error.

If the stack is not empty, then stack top is the address of the top element in the stack. If the stack is empty, then stack top must be stack base - 1.

A stack can be created and initialized by allocating a region of memory, setting stack base to the first word and stack limit to the last word, and setting stack top to stack base - 1.

The push instruction pushes an element onto a stack. It is RRR format, and its general form is:

push   Rd,Ra,Rb

• Rd = stack data: value to be pushed, unchanged
• Ra = stack top: incremented unless stack was full
• Rb = stack limit: unchanged
• R15 condition code indicates stack overflow
• System interrupt request register indicates stack overflow

This instruction pushes the word in Rd onto a stack with stack top in Rd and stack limit in Rb, provided that the stack is not full. The push stores the data word in Ra into memory and increments stack top Rd. If the stack is full, nothing is stored into memory and a stack overflow error is indicated in the condition code and interrupt request registers; an interrupt will occur if interrupts are enabled and the stack mask bit is set. The operational semantics is:

if Ra < Rb
  then Ra := Ra + 1; mem[Ra] := Rd
  else R15.sovfl := 1, req.sovfl := 1

If Rd = Rb this means the stack completely fills the region of memory allocated for the stack, and there is no space to store a new element. In this case, the push instruction does not store Ra, it doesn't modify Rd, it doesn't modify memory outside the block, and it doesn't overwrite data in the stack. Instead, the instruction indicates a stack overflow by setting the sovfl (stack overflow) bit in the condition code (R15), and it also sets the stack fault bit in the interrupt request register. If interrupts are enabled and the stack fault bit is set in the interrupt mask register, then an interrupt will occur after the push instruction completes. There will be no interrupt if interrupts are disabled, or the stack fault bit is not set in the mask register.

The push instruction removes an element onto a stack and returns it. The instruction is RRR format, and its general form is:

pop    Rd,Ra,Rb

• Rd = stack data: destination for the popped stack element
• Ra = stack top: decremented unless stack was empty
• Rb = stack base: unchanged
• R15 condition code indicates stack underflow
• System interrupt request register indicates stack underflow

This instruction pops the word from a stack with stack top in Ra and stack base in Rb, provided that the stack is not empty. The pop loads the top element of the stack into Rd and decrements stack top. If the stack is empty, stack top is not decremented, Rd is not modified, and a stack underflow error is indicated in the condition code and interrupt request registers; an interrupt will occur if interrupts are enabled and the stack mask bit is set. The operational semantics is:

if Ra >= Rb
  then Rd := mem[Ra]; Ra := Ra - 1
  else R15.suvfl := 1, req.suvfl := 1

The top instruction returns the top element on a stack but does not remove it. The instruction is RRR format, and its general form is:

top    Rd,Ra,Rb

• Rd = stack data: destination for the top element of the stack; unchanged if stack is empty
• Ra = stack top: unchanged
• Rb = stack base: unchanged
• R15 condition code indicates stack underflow
• System interrupt request register indicates stack underflow

This instruction loads the element at stack top into Rd, provided that the stack is not empty. If the stack is empty, Rd is not modified and a stack underflow error is indicated in the condition code and interrupt request registers; an interrupt will occur if interrupts are enabled and the stack mask bit is set. The operational semantics is:

if Ra >= Rb
  then Rd := mem[Ra]
  else R15.suvfl := 1, req.suvfl := 1

When a program calls a procedure it is usually necessary to save the state of the caller in a data structure called a stack frame. (This is not necessary during a "tail call".) The stack frame is pushed onto the execution stack. When the procedure returns, the contents of the stack frame need to be loaded back into the registers. These operations can be performed by ordinary store instructions (for procedure call) and load instructions (for procedure return). However, this often requires a significant number of instructions.

The save and restore instructions transfer a block of data between registers and memory, making it easier to use stack frames. These instructions are analogous to store and load, but they store or load multiple words, not just an individual word.

• save stores a sequence of adjacent registers into a block of contiguous memory locations.
• restore is the opposite: it loads the block of memory into the registers.

For both instructions, the sequence of registers is specified by giving the first and last register. The starting address of the memory block is specified by an effective address of the form offset[Reg], where Reg is any register (e.g. R4, R13, etc) and offset is a number between 0 and 255.

Normally \(d \leq e\), in which case the number of registers to be saved is \(e-d + 1\). If \(d > e\), the instruction will do nothing. The base register \(R_f\) should not lie within the group of registers to be saved or restored.

The first register to be saved is \(R_d\), and the last register to be saved is \(R_e\). The instruction always stores at least one register. If \(d = e\), for example save R5,R5,0[R14] then only R5 is stored. If \(d < e\) then the register numbers wrap around For example,

There is an important restriction with save and restore: the displacement is limited to a small natural number between 0 and 255. (Recall that for load and store, the displacement can be as large as 65,535.) The reason for this is that the save and restore instructions are EXP format and the offset is represented by an 8-bit field (whereas load and store are RX format and the displacement is a 16-bit word).

The instruction is EXP format, and the offset is limited to 8 bits, because it is specified in the gh field, which is the rightmost 8 bits of the second word of the instruction. The secondary opcode is 9, which is in the ab field of the first word of the instruction.

The save instruction performs a sequence of stores, which copy the contents of a sequence of registers into consecutive memory locations.

• \(\mathsf{mem}[R_f+gh] := R_d\)
• \(\mathsf{mem}[R_f+gh+1] := R_{d+1}\)
• \(\mathsf{mem}[R_f+gh+2] := R_{d+2}\)
• \(\ldots\)
• \(\mathsf{mem}[R_f+gh+e-d] := R_e\)

For example, the following instruction will save registers R3 through R9 into memory starting at address 6 + R13. Its machine language code is e30b 9d06.

save   R3,R9,6[R13]

This instruction is equivalent to a sequence of store instructions:

store   R3,6[R13]
store   R4,7[R13]
store   R5,8[R13]
store   R6,9[R13]
store   R7,10[R13]
store   R8,11[R13]
store   R9,12[R13]

As this example shows, using save and restore can make procedure calls more concise and readable as well as less error-prone.

This restore instruction has the same operands as save, and it performs a sequence of loads corresponding to the stores performed by save.

For example, consider this instruction:

restore  R3,R10,4[R14]

The effect is equivalent to

load  R3,4[R14]
load  R4,5[R14]
load  R5,6[R14]
load  R6,7[R14]
load  R7,8[R14]
load  R8,9[R14]
load  R9,10[R14]
load  R10,11[R14]

Suppose a stack frame was created by the save example above. To restore the registers from the stack frame, use:

restore R3,R9,6[R13]  ; e30b 9d06. store R3-R9 starting at 6[R13]

It is equivalent to a sequence of store instructions:

load   R3,6[R13]
load   R4,7[R13]
load   R5,8[R13]
load   R6,9[R13]
load   R7,10[R13]
load   R8,11[R13]
load   R9,12[R13]

restore R3,R5,6[R13]  ; e30c 5d06. load R3-R5 starting at 6[R13]

This is equivalent to a sequence of load instructions:

load    R3,6[R13]
load    R4,7[R13]
load    R5,8[R13]
load    R6,9[R13]

The restore instruction copies a sequence of consecutive memory locations starting from the effecive address into a sequence of adjacent registers. The index register (R14 in this example) is not changed. Restore is equivalent to a fixed sequence of load instructions; its purpose of restore is to restore the state of registers from memory after a procedure call or a context switch.

The instruction restore Re,Rf,gh[Rd] copies the contents of memory at consecutive locations beginning with mem[gh+Rf] into registers Re, Re+1, …, Rf.