Sigma16 User Guide

A trap break is a trap instruction whose first operand register contains the value 4. The other operand registers are ignored. When this instruction executed, the emulator will stop execution, and you can resume execution later.

Suppose you want to check what the load instruction is doing in this code:

...
add    R1,R2,R3
load   R4,x[R1]
...

Insert a breakpoint just before the instruction you want to examine. The breakpoint requires two instructions. The first instruction loads the break code into some register (say R9 but it doesn't matter which), and the second instruction is a trap which actually performs the break. The first operand is the register that contains the break code, and the other two operands are ignored, so we can just use R0.

...
add    R1,R2,R3
lea    R9,4       ; R9 := trap break code
trap   R9,R0,R0   ; breakpoint
load   R4,x[R1]
...

Now you can run the program at full speed, but when it executes the trap instruction, the emulator will stop. Since the trap instruction has just executed, it will be highlighted in red, and the instruction you're interested in – the load – will be highlighted in blue. You can single step for a while, and click Run again at any time to resume full speed execution.

A common technique is to put a trap break at the beginning of a loop. By clicking Run repeatedly, you can step through the loop iterations.

For an example of a long running program with a trap break, see Examples / Core / Testing / Looper.

An external break tells the emulator to perform a breakpoint without modifying the program. Use these steps to set an external break:

1. Find the address of the instruction to stop at: look at the assembly listing, find the instruction, and the listing gives its address.
2. Go to the processor page, click Boot and then click Breakpoint.
3. A small window will appear; type in the breakpoint address. It must be a hexadecimal address in assembly language format: it must begin with a $ and then contain four hex digits. No other characters may be present, not even white space.
4. Click Refresh. This parses the address you entered and remembers it. (If you change the address in the window, click Refresh again.)
5. Click Enable. This turns on the breakpoint.
6. Click CLose. The breakpoint popup window will disappear so you can see the Processor again.

Now click Run and the program will execute at full speed. When the pc register is equal to the breakpoint address, the emulator will stop. Then you can Step or Run to continue execution.

As long as the breakpoint is enabled, execution will stop every time that location is encountered. To prevent this, open the breakpoint popup again and click Disable.

RRR instructions are represented in one word comprising four 4-bit fields. Each field contains 4 bits representing a binary number between 0 and 15.

• op (bits 15 to 12) is the operation code, usually called opcode. This determines the operation to be performed. If the opcode is between 0 and 12 it specifies an RRR instruction. An opcode greater than 12 indicates an expanding opcode: the instruction is not RRR but one of the other formats, and it has a secondary opcode that specifies precisely which instruction it is. This is explained in the sections on RX and EXP formats.
• d (bits 11 to 8) is the destination register; the register where (in most cases) the result will be loaded.
• a (bits 7 to 4) is the register containing the first operand.
• b (bits 3 to 0) is the register containing the second operand.

In most cases, an RRR instruction takes two operands in registers specified by the a and b fields and produces a result which is loaded into the register specified by the d field. A typical example of an RRR instruction is add R4,R9,R2, which adds the contents of registers R9 and R2, and loads the result into R4. It's equivalent to R4 := R9 + R2. The opcode for add is 0, so the machinen language code for this instruction is 0492.

RX instructions specify a memory location as well as a register operand. The machine language representation is two words:

Here is RX

The RX instruction format is used for instructions that use a memory address, which is specified by an index register and a displacement. The name of the format describes briefly the two operands: a register (R) and an indexed memory address (X).

An RX instruction contains two operands: one is a memory address, and the other is a register. Typical RX instructions are loads, stores, and jumps. The instruction consists of two consecutive words. The first has the same format as an RRR instruction, with four fields: op, d, sa, sb. The second word is a single 16-bit binary number, and is called the displacement.

An RX instruction is represented by two words, with the following fields: op=15, b contains the secondary opcode which specifies which RX instruction it is, d is the destination, a is the index register, and the second word is a 16 bit constant called the displacement (often written disp for short).

• op field (bits 0-3 of ir) is f for all RX instructions
• d field (bits 4-7 of ir) has several uses
• a field (bits 8-11 of ir) is index register for effective address
• b field (bits 12-15 of ir) is secondary opcode
• disp (displacement) is the second word of the instruction
• ea (effective address) = displacement + r[a]

The memory address is specified in two parts: an index register and the displacement. The index register is specified in the sa field. In assembly language, the notation used is number[reg], where the number is the value of the displacement, and the reg is the index register. Thus $20b3[R2] means the address has displacement $20b3 and the index register is R2.

When the machine executes an RX instruction, it begins by calculating the effective address. This is abbreviated "ea", and its value is the sum of the displacement and the contents of the index register.

RX instructions are represented in two words, and they use an "expanding opcode". That is, the op field of the first word of the instruction contains the constant f (the bits 1111) for every RX instruction, and the sb field is used to hold a secondary opcode indicating which RX instruction it is.

The register operand is specified in the d field. For several RX instructions, this is indeed the destination of the instruction: for example, load places data into Rd. However, a few RX instructions use the d field differently (see, for example, the conditional jump instructions).

The memory address is specified using the sa field and the displacement, which is the entire second word of the instruction.

The bits of a word are indexed from right to left, starting with 0. The least significant (rightmost) bit has index 0, and the most significant bit (leftmost) has index 15.

The notation \(x.i\) means the bit with index \(i\) in the word \(x\), for \(0 \leq i \leq 15\). For example, \(x.0\) is the rightmost bit and \(x.15\) is the leftmost bit. When used in an instruction, a bit index is specified as a 4-bit binary number \(i\) such that \(0 \leq i \leq 15\).

The following table shows the indices of all the bits in a word. The vertical bars break the word into groups of 4 bits. This grouping corresponds to the representation of the word in hex notation.

\[\fbox{$\ x_{15}\> x_{14}\> x_{13}\> x_{12} \ \vert\ x_{11}\> x_{10}\> x_{9}\> x_{8} \ \vert\ x_{7}\> x_{6}\> x_{5}\> x_{4} \ \vert\ x_{3}\> x_{2}\> x_{1}\> x_{0} \ $}\]

A bit field is a contiguous sequence of bits in a word. It is specified by two numbers: the index of the leftmost bit in the field, and the size of the field.

The natural numbers are \(0, 1, 2, \ldots\). All natural numbers are nonnegative. Natural numbers are represented in binary. Sigma16 uses natural numbers to represent memory addresses. The binary value of an $n$-bit generic word \(x\) is

\[binval (x) = \sum_{0 \leq i < n} x_i * 2^i\]

For a word of 16 bits, natural numbers are restricted to the range from 0 through \(2^{16}-1\); that is, from 0 through 65,535. For a double word (32 bits), natural numbers are restricted to the range from 0 through \(2^{32}-1\); that is, from 0 through 4,294,967,295.

A natural number (and hence a binary number) cannot be negative. If you need numbers that can be negative or positive, you must use an integer. The arithmetic instructions in Sigma16 operate on integers, but address arithmetic is performed in binary.

Integers are represented using two's complement notation. If the leftmost (most significant) bit of a word is 0, its two's complement value is the same as its binary value. If the leftmost bit is 1, the two's complement value is negative. Any two's complement number can be negated by inverting all the bits (replace 0 by 1 and vice versa) and then adding 1, discarding any overflow.

For example, consider \(x\) = 1111 1010. Since the leftmost bit is 1, we know that \(x < 0\). We can negate \(x\) by inverting the bits, obtaining 0000 0101. Adding 1 gives 0000 0110 which is 6. Since \(-x = 6\), we conclude that \(x = -6\).

Assembly language provides several notations for expressing the value of a word. If a numeric value is out of range it is truncated.

• An unsigned integer between 0 and 65,535 (2¹⁶ - 1)
• A signed integer between -32,768 and 32,767 (-2¹⁵ and 2¹⁵ - 1)
• A 4-digit hexadecimal constant, where the digits are 0-9 a-f. Sometimes, when the context is clear, this is written as just the hex digits (e.g 3b2f). In assembly language programs, hex constants are written with a preceding $ sign (e.g. $3b2f). This is necessary to avoid ambiguity: 1234 is a decimal number and $1234 is a hexadecimal number. In contexts where there is no ambiguity, the $ may be omitted: for example, the user interface shows register and memory contents as hexadecimal without the leading $.

The register file is a set of 16 general registers that hold a 16 bit word. A register is referenced by a 4-bit binary number. In assembly language, we use the notations R0, R1, R2, …, R9, R10, R11, R12, R13, R14, R15 to refer to the registers. The state of the register file can be written as a table showing the value of each register:

Sigma16 is a load/store style architecture; that is, it does not combine memory accesses with arithmetic. All calculations are carried out in the register file, and explicit load and store instructions must be used to copy data between the memory and the register file.

There are some programming conventions that use certain registers for special purposes. The hardware does not enforce, or even know about, these conventions, and you do not have to follow the conventions in programming. However, it is necessary to obey the conventions in order to use the standard software libraries in your program. See the section on Programming for a discussion of these standard usage conventions.

There are several instruction control registers that enable the processor to keep track of the state of the running program. These registers are rarely used directly by the machine language program, but they are essential for keeping track of the execution of the program, and some instructions use them directly.

(Will be implemented in future version)

The RRR format is used for instructions that perform calculations in the registers, without using memory.

An instruction in RRR format is one word containing four 4-bit fields called op, d, a, b. The op field is the operation code. If \(0 \leq op \leq 13\), its value specifies which RRR instruction this is. If \(13 < op\), this means the instruction "escapes" to another addressing mode. If \(op=15\) the instruction is RX format, and \(op=14\) means it is EXP format.

Most RRR instructions have two operand registers specified in the a and b fields. They perform a calculation on the values in these registers, and the result is written into the d register (d for destination).

The RX format is used for instructions that access the memory. There are two operands: a memory address and a register. The memory address is specified using two fields: a constant (called the displacement) and a register (called the index register).

An RX instruction consists of two words. The first has the same format as RRR. The op field is 15, which means "this instruction has RX format". A secondary operation code is needed to specify which RX instruction this is, this is given in the b field. The d field is the destination register, and the a field is the index register. There is only one operand register for RX instructions, since the b field is needed for the secondary operation code.

The second word consists of one 16-bit field called the displacement (abbreviated as disp).

The index register Rb and the displacement together specify the effective address. The assembly language syntax for the effective address is disp[Rb], and its value is \(\mathrm{disp} + \mathrm{Rb}\). For example, suppose R4 contains 7 when the following instruction is executed:

load  R2,5[R4]

The address operand is 5[R4], where the displacement is 5 and the index is R4. When the instruction executes, the effective address is \(5 + \mathrm{R4} = 5 + 7 = 12\), or $000c.

The displacement is a constant given in the instruction, but the index register is variable. Since R0 always contains 0, the effective address for disp[R0] is the value of disp.

The displacement is represented in binary, and the effective address is calculated in binary, not in two's complement. Thus the effective address of ffff[R0] is the (positive) address of the last word in memory – it isn't a negative number.

The EXP instructions provide more complex operations, and they belong to the Standard architecture. (The Core architecture uses only RRR and RX). An EXP instruction consists of two words.

The first word has the same op and d fields as RRR and RX. The op field contains 14 (hex e), which indicates that the instruction is EXP format. The a and b fields are treated as one 8-bit natural number, which is the secondary operation code. This provides for the possibility of up to 256 EXP format instructions, which enables new experimental instructions to be defined.

The second word contains for 4-bit fields. Each of these may contain either a register number or a short 4-bit number, depending on the instruction.

We usually write instructions in assembly language (sub R3,R12,R9) but the computer executes machine langugae (13c9). When each instruction is described below, an example is given showing a typical use of the instruction, along with the general form of the assembly language instruction.

The general form uses the machine language field names to show where each piece of the instruction goes in the machine code. The instruction format is also given, along with any constant fields.

For example, here is the general form of the logicu instruction:

logicu  Rd,e,Rf,g,h     ; Rd.e := h (Rd.e, Rf.g)
EXP op=#e ab=$14

The format is EXP, so the instruction has all the fields of the EXP format: op, d, ab, e, f, g, h. There are two constant fields: op is $e, and ab is $14. The values of the other fields are given in the general form of the assembly language. The operands Rd and Rf refer to registers, and those register numbers go into the d and f fields of the instruction. The e, g, and h fields are given as numbers in the assembly language. (The assembly language convention is to give constants in decimal notation, not hexadecimal.)

Example:

logicu  R7,5,R2,13,xor ; R7.5 := R7.5 xor R2.13
e714 52d6

The load effective address instruction lea Rd,disp[Rx] calculates the effective address of the operand disp[Rx] and places the result in the destination register Rd. The effective address is the binary sum disp+Rx.

The load instruction load Rd,disp[Rx] calculates the effective address of the operand disp[Rx] and copies the word in memory at the effective address into the destination register Rd. The effective address is the binary sum disp+Rx.

------------–— ------------------------------------–— general form load Rd,disp[Ra] effect reg[Rd] := mem[disp+reg[Ra]] machine format RX assembly format RX ------------–— ------------------------------------–—

Examples

load  R12,count[R0]   ; R12 := count
load  R6,arrayX[R2]   ; R6 := arrayX[R2]
load  R3,$2b8e[R5]    ; R3 := mem[2b8e+R5]

The store instruction store Rd,disp[Rx] calculates the effective address of the operand disp[Rx] and the value of the destination register Rd into memory at the effective address. The effective address is the binary sum disp+Rx.

------------–— ------------------------------------–— general form store Rd,disp[Ra] effect mem[disp+reg[Ra]] := reg[Rd] machine format RX assembly format RX ------------–— ------------------------------------–—

Store copies the word in the destination register into memory at the effective address. This instruction is unusual in that it treats the "destination register" as the source of data, and the actual destination which is modified is the memory location.

Most instructions take data from the rightmost operands and modify the leftmost destination, just like an assignment statement (x := y+z). However, the store instruction operates in the opposite direction. The reason for this has to do with the circuit design of the processor. Although the "left to right" nature of the store instruction may look inconsistent from the programmer's point of view, it actually is more consistent from the deeper perspective of circuit design.

Examples

store  R3,$2b8e[R5]
store  R12,count[R0]
store  R6,arrayX[R2]

Three instructions (push, pop, top) support operations on a stack represented as an array of contiguous elements, where the stack grows from lower to higher addresses. These instructions provide safe operations: they never overwrite memory outside the stack, and they indicate stack underflow and overflow by setting the condition code and optionaly performing an exception.

A stack is represented by three addresses, which are provided to the push, pop, and top instructions in registers:

• The stack base is the address of the first word allocated for the stack.
• The stack limit is the address of the last word allocated for the stack.
• The stack top is the address of the stack element that was pushed most recently.

Although three addresses are required to characterise the state of a stack, each individual stack instruction (push, pop, top) requires only two of those addresses. These are supplied as the Ra and Rb operands, while Rd is used to supply or receive the data value.

The maximum number of elements the stack may contain is stack limit - stack base + 1. Normally, stack limit is greater than stack base. If they are equal, there is only one word allocated for the stack (which is generally not useful), and if stack base > stack limit then no memory at all is allocated and every stack operation will signal an underflow or overflow error.

If the stack is not empty, then stack top is the address of the top element in the stack. If the stack is empty, then stack top must be stack base - 1.

A stack can be created and initialized by allocating a region of memory, setting stack base to the first word and stack limit to the last word, and setting stack top to stack base - 1.

When a program calls a procedure it is usually necessary to save the state of the caller in a data structure called a stack frame. (This is not necessary during a "tail call".) The stack frame is pushed onto the execution stack. When the procedure returns, the contents of the stack frame need to be loaded back into the registers. These operations can be performed by ordinary store instructions (for procedure call) and load instructions (for procedure return). However, this often requires a significant number of instructions.

The save and restore instructions transfer a block of data between registers and memory, making it easier to use stack frames. These instructions are analogous to store and load, but they store or load multiple words, not just an individual word.

• save stores a sequence of adjacent registers into a block of contiguous memory locations.
• restore is the opposite: it loads the block of memory into the registers.

For both instructions, the sequence of registers is specified by giving the first and last register. The starting address of the memory block is specified by an effective address of the form offset[Reg], where Reg is any register (e.g. R4, R13, etc) and offset is a number between 0 and 255.

Normally \(d \leq e\), in which case the number of registers to be saved is \(e-d + 1\). If \(d > e\), the instruction will do nothing. The base register \(R_f\) should not lie within the group of registers to be saved or restored.

The first register to be saved is \(R_d\), and the last register to be saved is \(R_e\). The instruction always stores at least one register. If \(d = e\), for example save R5,R5,0[R14] then only R5 is stored. If \(d < e\) then the register numbers wrap around For example,

There is an important restriction with save and restore: the displacement is limited to a small natural number between 0 and 255. (Recall that for load and store, the displacement can be as large as 65,535.) The reason for this is that the save and restore instructions are EXP format and the offset is represented by an 8-bit field (whereas load and store are RX format and the displacement is a 16-bit word).

The instruction is EXP format, and the offset is limited to 8 bits, because it is specified in the gh field, which is the rightmost 8 bits of the second word of the instruction. The secondary opcode is 9, which is in the ab field of the first word of the instruction.

The instruction add Rd,Ra,Rb has operands Ra and Rb and destination Rd. It fetches the operands Ra and Rb, calculates the sum Ra + Rb, and loads the result into the destination Rd. The effect is Rd := Ra + Rb. For example, add R5,R12,R2 performs R5 := R12 + R3.

The add instruction is RRR format with opcode=0. Given destination Rd and operands Ra and Rb (where d, a, b are hex digits), add Rd,Ra,Rb is reprseented by 0dab.

Code Assembly Effect –— -----------–— -------------–— 062c add R6,R2,R12 ; R6 := R2 + R12 0d13 add R13,R1,R3 ; R13 := R1 + R3

The add instruction sets both the destination register and the condition code. Flags in the condition code indicate overflow, carry, and sign of the result.

----–— ----------------–— R15.ccG result > 0 (binary) R15.ccg result > 0 (two's complement) R15.ccE result = 0 R15.ccl result <tc 0 (two's complement) R15.ccV overflow (binary) R15.CCv overflow (two's complement) R15.CCc carry output ----–— ----------------–—

The bits in a word are numbered from right to left, starting at bit index 0 in the rightmost (least significant) position, up to index 15 at the leftmost (most significant) position. The notation x.n denotes the bit in x with index n.

A field is a consecutiave sequence of bits within a word. A field is specified with the index of the leftmost bit in the field, along with the size of the field. For example, the field in x with index 9 and size 3 consists of the bits x.9 x.8 x.7.

add R1,R2,R3    ; R1 := R2 + R3

The instruction add Rd,Ra,Rb has operands Ra and Rb and destination Rd. It fetches the operands Ra and Rb, calculates the sum Ra + Rb, and loads the result into the destination Rd. The effect is Rd := Ra + Rb. For example, add R5,R12,R2 performs R5 := R12 + R3.

The add instruction is RRR format with opcode=0. Given destination Rd and operands Ra and Rb (where d, a, b are hex digits), add Rd,Ra,Rb is reprseented by 0dab.

The add instruction can be used for both binary addition (on natural numbers) and for two's complement addition (on signed integers).

• 16-bit natural numbers are unsigned integers 0, 1, 2, …, 65535. If two natural numbers are added, the result is a natural number (the result cannot be negative). If the result is 65536 or larger, it cannot be represented as a 16 bit binary number. If this happens, the destination register is set to the lower 16 bits of the true result, and the binary overflow flag is set in the Condition Code.
• 16-bit two's complement numbers are signed integers -32999?, …, -1, 0, 1, …, 32???. If two signed integers are added, the result is a signed integer. If the result is less than -32000 or greater than 32000, then the result cannot be represented as a 16 bit two's complement number. If this happens, the destination register is set to the lower 16 bits of the true result, and the two's complement overflow flag is set in the Condition Code. Furthermore, the overflow flag is set in the req register. If interrupts are enabled and the overflow flag is 1 in the mask register, then an interrupt will occur immediatelhy after the add instruction executes.

The add instruction can be used for both binary addition (on natural numbers) and for two's complement addition (on signed integers).

• 16-bit natural numbers are unsigned integers 0, 1, 2, …, 65535. If two natural numbers are added, the result is a natural number (the result cannot be negative). If the result is 65536 or larger, it cannot be represented as a 16 bit binary number. If this happens, the destination register is set to the lower 16 bits of the true result, and the binary overflow flag is set in the Condition Code.
• 16-bit two's complement numbers are signed integers -32999?, …, -1, 0, 1, …, 32???. If two signed integers are added, the result is a signed integer. If the result is less than -32000 or greater than 32000, then the result cannot be represented as a 16 bit two's complement number. If this happens, the destination register is set to the lower 16 bits of the true result, and the two's complement overflow flag is set in the Condition Code. Furthermore, the overflow flag is set in the req register. If interrupts are enabled and the overflow flag is 1 in the mask register, then an interrupt will occur immediatelhy after the add instruction executes.

Example: sub R1,R2,R3 ; R1 := R2 - R3

This instruction is similar to add; the only difference is that it calculates R2-R3 and places the result in R1. The effect on the condition code is the same as for add.

The instruction sub Rd,Ra,Rb has operands Ra and Rb and destination Rd. It fetches the operands Ra and Rb, calculates the difference Ra - Rb, and loads the result into the destination Rd. The effect is Rd := Ra - Rb. For example, sub R5,R12,R2 performs R5 := R12 - R3.

The sub instruction is RRR format with opcode=1.

Code Assembly Effect –— -----------–— -------------–— 162c sub R6,R2,R12 ; R6 := R2 - R12 1d13 sub R13,R1,R3 ; R13 := R1 - R3

In addition to setting the destination register, the sub instruction sets several bits in the condition code R15 and may set a bit in the req register.

----–— ----------------–— R15.ccG result > 0 (binary) R15.ccg result > 0 (two's complement) R15.ccE result = 0 R15.ccl result < 0 (two's complement) R15.ccV overflow (binary) R15.CCv overflow (two's complement) R15.CCc carry output R15.ccf logicc instruction function result ----–— ----------------–—

Example: mul R1,R2,R3 ; R1 := R2 * R3

The multiply instruction mul Rd,Ra,Rb calculates the integer (two's complement) product of the operands Ra and Rb, and places the result in the destination register Rd. The mul instruction does not produce the natural (binary) product.

If the magnitude of the product is too large to be representable as a 16 bit two's complement integer, this is an overflow. If overflow occurs, the integer overflow bit is set in the condition code (F15) and the integer overflow bit is also set in the interrupt request register (req), and the lower order 16 bits of the product are loaded into Rd.

----–— ----------------–— R15.ccg result > 0 (two's complement) R15.ccE result = 0 R15.ccl result < 0 (two's complement) R15.CCv overflow (two's complement) R15.CCc carry output ----–— ----------------–—

Example: div R1,R2,R3 ; R1 := R2 / R3, R15 := R2 rem R3

Unlike the other arithmetic operations, the divide instruction div Rd,Ra,Rb produces two results: the quotient Ra / Rb and the remainder Ra rem Rb. It loads the quotient into the destination register Rd, and the remainder is loaded into R15.

If the destination register Rd is actually R15, then the quotient is placed in R15, and the remainder is discarded.

The divide instruction doesn't set the condition code, since R15 is used for the remainder. Therefore there is no condition code bit to indicate division by 0. However, it is easy for a program to detect a division by 0.

• (Explicit test for error) The program can compare the divisor with 0 before or after executing the divide instruction, and jump to an error handler if the divisor is 0. This is similar to testing the condition code after an add, sub, or mul instruction, but it does require two instructions: a compare followed by a conditional jump. For example:

div    R1,R2,R3       ; R1 := R2/R3, R15 := R2 rem R3
cmp    R3,R0       ; Did we divide by 0?
jumpeq zeroDivide[R0] ; If yes, handle error

• (Exception) The program can detect division by 0 using an interrupt. To do this, enable interrupts and enable the interrupt mask for division by 0. See the section on Interrupts. This approach does not require a compare or jump instruction for each division.

The compare instruction cmp Ra,Rb compares the values in the operand registers Ra and Rb, and then sets flags in the condition code (R15) to indicate the result. The notation R15.i means bit i in R15; thus R15.0 is the leftmost bit of R15. The instruction performs both natural number comparison (binary) and integer comparison (two's complement). The resulting flags are

• binary less than (L) in R15.0
• two's complement less than (<) in R15.1
• equal in R15.2
• binary greater than (G) in R15.3
• two's complement greater than (>) in R15.4

The result of a cmp instruction can be used to control a conditional jump. The jumpc0 instruction jumps is a specified bit of R15 is 0, and the jumpc1 instruction jumps if a specified bit is 1.

Pseudoinstructions provide the most common cases; for example jumple jumps if the condition code indicates that a comparison produced either integer less-than or equal. A common pattern is a cmp followed by a jump pseudoinstruction, for example:

cmp     R4,R9      ; compare R4 with R9
jumpgt  abc]R0]    ; if R4 > R9 then goto abc

The addc instruction performs a binary addition with carry propagation. It adds the two operand registers and the carry bit in the condition code register, R15. The sum is loaded into the destination register Rd and the carry output is written back into the carry bit, overwriting its previous value. Overflow is not possible with this instruction.

muln   Rd,Ra,Rb

The muln instruction calculates the product of two natural numbers in Ra and Rb. The result is 32 bits; the leftmost 16 bits (the most significant part) is loaded into R15, and the rightmost 16 bits (the least significant part) is loaded into Rd. If Rd is R15, the most significant part is discarded.

divn   Rd,Ra,Rb

The divn instruction divides two natural numbers: dividend / divisor. All the numbers – numerator, denominator, quotient, remainder – are natural numbers represented in binary.

• The dividend is a 32 bit natural number; its leftmost 16 bits are in R15 and the rightmost 16 bits are in Ra. Thedenominator is in Rb.
• Two results are produced: a 32-bit quotient anda 16-bit remainder.
• The leftmost 16 bits of the quotient are placedin R15 (replacing the leftmost part of the dividend). The rightmost16 bits of the quotient are placed in Rd.
• The remainder is placed in Ra, overwriting the least significant half of the dividend operand

The brf instruction is Branch forward, and the brb instruction is branch backward.

The operand is a 16-bit natural number called the offset. This is added to (brf) or subtracted from (brb) the current value of the pc register. Since the pc is incremented as the instruction is fetched, an offset of 0 refers to the instruction after the brf/brb.

a    brf  3
     add  R0,R0,R0  ; brf 0 would go here
     add  R0,R0,R0  ; brf 1 would go here
     add  R0,R0,R0  ; brf 2 would go here
b    add  R0,R0,R0  ; the instruction a actually goes here

Normally the operand is expressed as a label rather than a constant.

a    brf  b
     add  R0,R0,R0
     add  R0,R0,R0
     add  R0,R0,R0
b    add  R0,R0,R0  ; the instruction a goes here

If the operand is expressed as a number (brf 3), the assembler uses the number in the machine instruction. However, if the operand is expressed as a lable (brf b), the assembler calculates the correct offset value and inserts that into the machine instruction.

In order to implement goto xyz, use brf xyz (branch forward) if xyz occurs after the branch instruction, and use brb xyz (branch backward) if xyz occurs before the branch.

There are four conditional branch instructions that perform a branch based on the value of a bit in a register. For example, brfc1 R7,3,dest is equivalent to "go to dest if bit 3 of R7 is 1". The instructions are:

• brfc0 - branch forward if the specified bit is 0
• brfc1 - branch forward if the specified bit is 1
• brbc0 - branch backward if the specified bit is 0
• brbc1 - branch backward if the specified bit is 1

These instructions are somewhat similar to jumpc0 and jumpc1, but there are two key differences:

• The branch instructions can use any bit in any register of the register file to determine whether the branch will take place, but the jump instructions can use only a bit in the condition code R15.
• The branch instructions are pc-relative, but the jump instructions give the absolute address of the destination.

These instructions perform a branch if a specified register is either equal to 0 (z), or not equal to 0 (nz). Equal to 0 means every bit in the register is 0; not equal to 0 means some bit in the register is 1. For example, brfnz R3,dest means "if R3 !=0 then goto dest".

• brfz - branch forward if zero
• brfnz - branch forward if not zero
• brbz - branch backward if zero
• brbnz - branch backward if not zero

The dispatch instruction implements a branch table. It provides an efficient way to implement a case statement using a binary code.

Suppose code is a variable that contains an integer, such that \(0 \leq code < 8\). The following set of instructions will branch to a specific destination depending on the value of the code.

load   R8,code[R0]  ; load a 3-bit binary code
dispatch R8,3,0       ; 38 dispatch 3-bit code
brf    caseA        ; if code=0 then goto caseA
brf    caseB        ; if code=1 then goto caseB
brf    caseC        ; if code=2 then goto caseC
brf    caseD        ; if code=3 then goto caseD
brf    caseE        ; if code=4 then goto caseE
brf    caseF        ; if code=5 then goto caseF
brf    caseG        ; if code=6 then goto caseG
brf    caseH        ; if code=7 then goto caseH

The dispatch instruction has three operands: a register code that specifies a binary code, an integer constant size that gives the number of bits in the code, and a fixed offset (which is usually 0).

• The instruction automatically uses size to mask the code, by performing a logical and. For example, if size is 3, it calculates code AND fff7. This ensures that the resulting code is not out of range: it is guaranteed to lie between 0 and \(2 ^ size - 1\).
• The instruction then performs a pc relative branch forward by a distance of 2 * code + offset. The multiplication by 2 ensures that a 2-word instruction can be placed in each position in the branch table.
• The branch table is normally a sequence of unconditional branch instructions, either brf or brb.

The invert function (also called not, logical negation) has one input.

The truth tables for and, or, xor have two inputs.

These aren't the only logic functions with two inputs. Every logic function with two inputs \(x\) and \(y\) can be defined by a truth table where we list all possible values for the inputs and give the corresponding result. Each input could be either 0 or 1. Since there are 2, there are \(2^2 = 4\) lines in the truth table.

The tables above give specific values, either 0 or 1, for each result. For example, the result column for the and function is (reading from top to bottom) 0001, while xor is 0110. For an arbitrary function, we can write the result column as \(abcd\) where each variable is either 0 or 1.

Since there are 4 variables, there are \(2^4\) possible settings of \((a,b,c,d)\) and consequently there are 16 Boolean logic functions that take two arguments. For example, if \((a,b,c,d) = (0,0,0,1)\) this is the truth table for and. if \((a,b,c,d) = (0,1,1,0)\) this is the truth table for xor.

The Sigma16 logic instructions take a 4-bit code that specifies the logic function by giving the values of \((a,b,c,d)\). In assembly language, the code is given as a decimal number between 0 and 15. The codes for the most common functions are:

Furthermore, the inv function can be treated as a 2-input function where the second argument is ignored.

The logicw instruction performs a bitwise logic operation on two operands: each bit of the result is obtained by performing the logic function on the corresponding bits of the two operands. The instruction allows an arbitrary logic function on two bits.

An arbitrary logic function of two variables is applied to the two operand registers Re and Rf, and the result is loaded into the destination register Rd. The function \(h\) is specified as described above; for example, 6 is the code for exclusive or. The general form is

logicw  Rd,Re,Rf,h     ; Rd := h (Re, Rf)
EXP. op=#e, ab=$12, g is ignored

The following example computes the xor of registers R1 and R2, and puts the result into R3.

lea     R1,$00ff[R0]  ; R1 := 00ff
lea     R2,$0f0f[R0]  ; R2 := 0f0f
logicw  R3,R1,R2,6    ; e312 1206. R3 := 0ff0

If you're using one of the most common logic functions, a pseudoinstruction is convenient and can make a program more readable. There are pseudoinstructions invw, andw, orw, xorw which have the same form as logicw except the function is specified by the pseudo operation and the function operand is omitted.

invw  R3,R4     ; R3 := invert R4
andw  R3,R4,R5  ; R3 := R4 and R5
or w  R3,R4,R5  ; R3 := R4 or R5
xorw  R3,R4,R5  ; R3 := R4 xor R5

A pseudoinstruction is not a machine instruction: the Sigma16 processor does not have an andw instruction. Instead, the assembler generates the logicw instruction corresponding to any of invw, andw, orw, xorw. The following assembly language statements generate exactly the same machine language:

logicw R5,R7,R2,1     ; R5 := R7 and R2
andw   R5,R7,R2       ; R5 := R7 and R2

If you prefer to use the actual machine instruction, rather than a pseudoinstruction, you can define a symbol for the logic function using an equ assembly directive. The symbol can then be used instead of the numeric code:

xor  equ   6
     ...
     logicw R5,R7,R2,xor   ; R5 := R7 xor R2

The logicr instruction allows you to specify any two operand bits and a destination bit, all within the same register. This is convenient when a program has a collection of Boolean flags kept in the same word. The general form is:

logicr  Rd,e,f,g,h  ; Rd.e := h (Rd.f, Rd.g)
EXP op=#e ab=$13

• Rd is the destination register, which also contains both source operands bits
• e is the index of the destination bit
• f is the index of the first argument bit
• g is the index of the second argument bit
• h is the logic function
• The instruction format is EXP, with primary e and secondary opcode $13.

Here is an example that performs logic on bits within R1, which is initialized to 0002. and calculates the logic or of bit 0 (which is 0) and bit 1 (which is 1). The result goes into bit 10, changing R1 from $0002 to $0402. The logic function or has code 7. Tthe operands are bits 9 and 2, and the result is placed into bit 3. The instruction says: within R1, perform logic function 7 on bits 0 and 1, and place the result in bit 10.

lea     R1,2[R0]     ; R1 := 0002, R1.0 = 0, R1.1 = 1
logicr  R1,10,0,1,or ; e113 a017. R1 := 0402, R1.10 = 1  

The op field of the first word of the machine language code for this example is 14 (hex e), indicating EXP format. The secondary operation code is $13, which is stored in the ab field. Since the general form is logicr Rd,e,f,g,h, we have \(d=1\), \(e=a\), \(f=0\), \(g=1\), and \(h=7\), so the machine language code is e113 a017.

If your program keeps a set of Boolean variables in one register, you can calculate Boolean expressions in that register with logicr.

Pseudoinstructions are provided for the most common bit logic functions. The operands are the same as for logicr, except the last operand is omitted, as the function is specified by the mnemonic.

invr    R1,3,9     ; R1.3 := inv R1.9
andr    R1,3,9,2   ; R1.3 := R1.9 and R1.2
orr     R1,3,9,2   ; R1.3 := R1.9 or R1.2
xorr    R1,3,9,2   ; R1.3 := R1.9 xor R1.2

The logicb instruction specifies two operand bits that may be in different registers. The result will overwrite the first operand bit. The general form is:

logicb  Rd,e,Rf,g,h     ; Rd.e := h (Rd.e, Rf.g)
EXP op=$e ab=$14

Example:

lea    R2,$0200[R0]   ; R2.9 := 1
lea    R7,$0000[R0]   ; R7.13 := 0
logicb R2,9,R7,13,xor ; e214 97d6. R2 := 0200, R2.9 := R2.9 xor R7.13

invb    R1,3,R2,9   ; R1.3 := inv R2.9
andb    R1,3,R2,9   ; R1.3 := R1.3 and R2.9
orub    R1,3,R2,9   ; R1.3 := R1.3 or R2.9
xorb    R1,3,R2,9   ; R1.3 := R1.3 xor R2.9

The invb pseudoinstruction is more flexible than invr, as it allows the operands to come from different registers. However, if you're doing logic operations in a word of Booleans, it may be clearer to write invb R9,3,7 than to write the equivalent invbr R9,3,R9,7.

The bit logic instructions have some useful special cases that don't appear to involve logic at all. These are supported by pseudoinstructions.

• setb Rd,e puts 1 into a specified bit: Rd.e : 1=.

setb   R4,7         ; R4.7 := 1

• clearb Rd,e puts 0 into the specified bit.

clearb R4,7         ; R4.7 := 0

• moveb Rd,e,Rf,g copies a bit from one register into a specified position in another register.

moveb  R4,7,R12,5   ; R4.7 := R12.5

• movebi Rd,e,Rf,g inverts a bit and copies it from one register into a specified position in another register.

moveb  R4,7,R12,5   ; R4.7 := R12.5

The shift instructions treat the operand as a string of bits, and move each bit a fixed distance to the left or right.

The instruction shiftl Rd,Ra,k shifts the value in the operand register Ra by h bits to the left, and the result is placed in the destination register Rd. The operand Ra is not modified. The leftmost k bits of the operand are discarded and the rightmost k bits of the result become 0. The general form is

shiftl Rd,Re,h
EXP op=$e, ab=$10, f,g are ignored

The instruction shiftr Rd,Re,k shifts the value in the operand register Ra by k bits to the right, and the result is placed in the destination register Rd. The operand Ra is not modified. During the shift, the rightmost k bits of the value are discarded and the leftmost k bits become 0. The general form is

shiftr Rd,Re,h
EXP op=$e, ab=$11, f,g are ignored

The following instruction shifts the value in R3 to the right by 5 bits and place the result in R2. The operand register R3 is not changed.

shiftr  R2,R3,5

The instruction format is EXP, and the assembly language statement format is RRKEXP

The instruction shiftl Rd,Ra,k shifts the value in the operand register Ra by k bits to the left, and the result is placed in the destination register Rd. The operand Ra is not modified. During the shift, the leftmost k bits of the value are discarded and the rightmost k bits become 0.

moveb  R4,7,R12,5   ; R4.7 := R12.5

• movebi Rd,e,Rf,g inverts a bit and copies it from one register into a specified position in another register.

moveb  R4,7,R12,5   ; R4.7 := R12.5

The extract and extracti instructions provide access to a field within a word. The extract instruction copies an arbitrary field of bits from a source register and inserts them into an arbitrary position in a destination register. The destination field is overwritten, while other bits in the destination register as well as all bits in the source register are unchanged.

The extracti instruction is similar, but it inverts the bits in the field before they are inserted into the destination.

These instructions are useful for systems programming. Emulators need to access instruction fields, software implementing floating point needs to access the parts of a floating point number, and networking software needs to decode message headers.

Bit indexing. Sigma16 indexes bit positions in a word from right to left, starting from 0. The least significant (rightmost) bit has index 0, and the most significant (leftmost) bit has index 15.

A bit field is a sequence of bits within a word. A field is specified using a pair of 4-bit natural numbers \(L,R\), where \(L\) is the index of the leftmost bit in the field and \(R\) is the index of the rightmost bit. The size of a field is \(\max (0, L-R+1)\). Consequently, if \(L < R\) the size is 0. For example:

• R8.6,4 is the field consisting of R8.6, R8.5, R8.4 and its size is 3.
• R8.11,11 is the field consisting of R8.11 and its size is 1.
• R8.15,0 is the field containing the entire contents of R8 and its size is 16.
• R8.5,7 is an empty field containing no bits; its size is 0

Machine language. The machine language format of extract and extracti is EXP, with the following fields:

• op = $e (escape to EXP)
• Rd = destination register
• ab = secondary opcode: $15 for extract and $16 for extracti
• Re = source register
• f = destination start index L
• g = destination end index R
• h = source start index L

The instruction specifies the destination field as \(f,g\). The field size S and the R index for the source are not specified in the instruction: only the leftmost index of the source field is specified explicitly as \(h\).

The sizes of the source and destination fields must be the same. The size and right index of the source are calculated as follows. The calculations verify that both the source and destination fields have the same size.

• The size \(S\) of a field specified by \(L,R\) is \(\max (0, L-R+1)\).
• In general, \(R = L - S + 1\).
• Destination field = Rd.f, Rd.f-1, …, Rd.g.
• Check that this works for destination: \(R = L - S + 1 = f - (f-g+1) + 1 = f - f + g - 1 + 1 = g\).
• Source field = Re.h, Re.h-1, …, Re.h-f+g
• Calculate \(R\) for source, which is not specified in the instruction. \(R = L - S + 1 = h - (f-g+1) + 1 = h - f + g - 1 + 1 = h - f + g\).

Assembly language. The assembly language operand format for extract is RkkRk, where R denotes a register number and k denotes a 4-bit constant. The general form of the instruction, in assembly language, is

extract Rd,f,g,Re,h

Effect. The effect is to overwrite each bit in the destination field with the corresponding bit in the source field:

Rd.f := Re.h
Rd.f-1 := Re.h-1
...
Rd.g := Re.h-f+g

For example, consider extract R14,9,7,R13,5, where \(f=9\), \(g=7\), \(h=5\). The field size is \(f-g+1 = 9-7+1 = 3\), so 3 bit assignments take place. The index of the rightmost bit in the source field = \(h-f+g = 5 -9 + 7 = 3\). Therefore the instruction performs the following bit assignments:

R14.9 := R13.5
R14.8 := R13.4
R14.7 := R13.3

; Assembly language: extract Rd,f,g,Re,h
; Effect:            Rd.f..g := Re.h..(h+g-f)
; EXP opcode:        e,15

; Example:           extract R2,11,8,R1,3
; Machine language:  e215 1b83

Example:

extract R2,7,4,R3,20
R2.7 := R3.20
R2.6 := R3.19
R2.5 := R3.18
R2.4 := R3.17

The extract and extracti instructions can be implemented using a combination of logic and shift instructions. They are included in the architecture for several reasons:

• These operations provide useful abstractions for writing interpreters and simulators.
• When used in an interpreter, bit field operations are executed frequently: they are a crucial part of the "inner loop". Therefore the efficiency of common bit field operations is important.
• The bit field instructions are easier to use and more readable than the corresponding logic and shifts.
• These instructions can be implemented efficiently in a digital circuit and this implementation is an interesting design problem.

The effect of an extract instruction can be described by writing each bit assignment individually, so there are size individual bit assignments. The notation R2.7 means the bit at position 7 in register R2. Using this notation, the example above performs the following bit assignments:

Relation to other instructions. Although extract performs a number of bit assignments, it is a single instruction and its execution time is a small fixed number of clock cycles. The execution time does not depend on the value of the field size, and extracting a large field doesn't require more time than extracting a small field. The hardware implementation of the instruction does not use an iteration to copy the bits; they are all copied in parallel in one clock cycle.

Any register may be specified for the source and destination. If they are the same, the effect is to move a bit field from one place to another within the register (this is not the same as a shift). If the destination is R0, the result is discarded and the instruction has no effect.

These instructions can be implemented using a combination of logic and shift instructions. They are included in the architecture for several reasons:

• These operations provide useful abstractions for writing interpreters and simulators.
• When used in an interpreter, bit field operations are executed frequently: they are a crucial part of the "inner loop". Therefore the efficiency of common bit field operations is important.
• The bit field instructions are easier to use and more readable than the corresponding logic and shifts.
• These instructions can be implemented efficiently in a digital circuit and this implementation is an interesting design problem.

Sigma16 has the flexibility required for "programming in the large". It provides modules, separate assembly, import and export, relocation, linking, executables, and booting. It also has special conventions that enable the user to skip those complications, and simply enter a standalone program, assemble it, and run it. The system is straightforward for beginners but allows a transition to realistic systems programming.

The assembler inputs a program in assembly language. This is called the source module. The assembler outputs an object module that contains the machine language code. The assembler also produces an assembly listing, which presents the program in a form useful for the programmer. The assembly listing shows the source code, the corresponding machine language, a symbol table, and any error messages. Finally, the assembler outputs a metadata module that enables the emulator to track the source statement corresponding to each instruction.

A simple program consists of just one source module that does not import anything. This is a standalone program, and assembling it produces an executable program. An executable program is an object module that does not require linking; it can be booted directly in the processor.

A larger program may consist of several source modules, including one main program. This requires use of the linker to combine the collection of object modules into a single executable program.

A value is a 16-bit word. An assembly language program uses expressions to denote values, but the actual underlying quantity is a value. A value consists of a word and several attributes:

• word is a natural number in the range from 0 to 2¹⁶-1.
• origin
  • if origin=Local, the value is defined within the module
  • if origin=External, the value is imported from another module
• movability
  • If movability=Relocatable, the value must be adjusted by the relocation constant when the module is relocated
  • If movability=Fixed, the value is not affected during relocation

Each line of source code is an assembly language statement. Unlike higher level languages, assembly language statements are not nested. There are three kinds of assembly language statement:

• Comments (blank lines, or lines beginning with ;)
• Code statements define instructions or constant data
• /Directives provide metadata but don't generate any code

An assembly language statement contains one or more fields. A field consists of non-space characters (with one exception: a space may appear in a string literal). Fields are separated from each other by one or more white space characters.

• Label. The label field is optional. If present, the label must be a name and it must begin in the first character of the line. If the first character is a space, then that line has no label.
• Operation. The operation field is an identifier that specifies an instruction or assembler directive. It must be preceded by one or more white space characters. Every statement (apart from a full line comment) must have an operation field.
• Operands. The operands field specifies operands for an instruction or arguments for assembly directives. There may be several operands, which must be separated by commas. Each type of statement (determined by the operation field) requires a specific syntax for the operands. Most instructions and assembler directives require operands, but some do not.
• Comment. All text that either (1) follows white space after the operands field, or (2) follows a semicolon (;), is a comment, and is ignored by the assembler. If one or more of the other fields (label, operation, operands) is missing, the comment must be preceded by a semicolon to prevent it from being interpreted as operands. The rule is: all text after a semicolon is a comment, and all text after white space following operands is a comment. A statement where the first non-space character is a semicolon is a full line comment. If the statement has no operands, then all text after the operation field is a comment. It is good practice always to begin a comment with a semicolon.

A directive is an assembly language statement that gives further information about how to translate the program to object code and how to link the code with other modules. Directirves specify metadata but they don't generate an instruction or constant data.

Object code is expressed in a textual language, so the object code is readable by a human (at least, by a human who understands machine language). For example, binary data is specified using four hexadecimal characters rather than a word of binary data.

The assembler and linker create metadata files which enable the emulator to show the assembly language statement corresponding to the instruction currently being executed. The metadata is not part of the machine language, and the emulator doesn't look at it in order to execute the program. It is entirely optional: the emulator can run a program without any metadata, although without it the emulator cannot display the current assembly language source statement. This section explains how the metadata works and the format of the files.

The emulator attempts to show the assembly language source as the program runs, and it highlights the current and next instruction. To do this, the emulator needs to have some information that isn't present in the object code. This extra information is supplied in a separate metadata file produced by the assembler and the linker.

An object file foo.obj.txt may have a corresponding metadata file foo.omd.txt ("object metadata"). An executable file foo.exe.txt may have a corresponding metadata file foo.xmd.txt ("executable metadata"). The format of the metadata is identical for object and executable; the reason for the distinction is that the user might have a program with main program foo.asm.txt, and later give the executable the same name foo. In that case, there will be separate metadata files for the object and the executable.

The metadata contains the source code in two forms: plain text and with html tags for highlighting the fields. In addition, the metadata contains a mapping from address to source code line number.

The metadata file format is parsed in order to populate several data structures that enable the emulator to The metadata contains the lines of text of the assembly listing. These lines contain the address, the object code at that address, and the assembly language source statement. Each line of the assembly listing appears t The emulator displays most lines of the assembly listing with the same field highlighting

A metadata file contains two sections: the ASmap followed by the source listing text. A metadata file must have the following contents:

\(a0,s0,a1,s1,a2,s2, ..., a_{n-1},s_{n-1}\)

When the pc contains address \(a_i\) then the source statement \(s_i\) should be displayed.

• fsmap n
• comma separated list of n numbers, which may be split into lines
• source n
• n lines of html giving the assembly listing. Each line appears twice: first a "plain" form, followed by a "decorated" form that contains html span elements for highlighting the fields of the text

Here is an example of a metadata file:

fasmap 17
14,14,15,15,16,16,17,17,18,19
19,20,20,21,21,22,24
source 32
<span class='ListingHeader'>Line Addr Code Code Source</span>
<span class='ListingHeader'>Line Addr Code Code Source</span>
   1 0000            ; Main: test linker
   1 0000           <span class='FIELDLABEL'> ... </span>

• GUI: selected module is main program and also receives the executable. All other modules are linked, and their object code is placed after that of the selected module. It is an error if any module has not been assembled. The order of the object code depends on the order of the modules in the module list, which is essentially arbitrary, except that the selected module always comes first in the executable.

Simple ("static") variabls need to be declared with a data statement, which also gives an initial value.

x  data  23

This means: allocate a word in memory for x and initialize it to 23. The data statements should come after the trap instruction that terminates the program

There are two ways to handle variables:

The statement-by-statement style: Each statement is compiled independently. The pattern is: load, arithmetic, store. Straightforward but inefficient.

The register-variable style: Keep variables in registers across a group of statements. Don't need as many loads and stores. More efficient. You have to keep track of whether variables are in memory or a register. Use comments to show register usage. Real compilers use this style. Use this style if you like the shorter code it produces.

We'll translate the following program fragment to assembly language, using each style:

x = 50;
y = 2*z;
x = x+1+z;

Statement-by-statement style

; x = 50;
     lea    R1,$0032   ; R1 = 50
     store  R1,x[R0]   ; x = 50

; y = 2*z;
     lea    R1,$0002   ; R1 = 2
     load   R2,z[R0]   ; R2 = z
     mul    R3,R1,R2   ; R3 = 2*z
     store  R3,y[R0]   ; y = 2*z

; x = x+1+z;
     load   R1,x[R0]   ; R1 = x
     lea    R2,1[R0]   ; R2 = 1
     load   R3,z[R0]   ; R3 = z
     add    R4,R1,R2   ; R4 = x+1
     add    R4,R4,R3   ; R4 = x+1+z
     store  R4,x[R0]   ; x = x+1+z

Register-variable style

; Usage of registers
;   R1 = x
;   R2 = y
;   R3 = z

; x = 50;
     lea    R1,$0032   ; x = 50
     load   R3,z[R0]   ; R3 = z
     lea    R4,$0002   ; R4 = 2
; y = 2*z;
     mul    R2,R4,R3   ; y = 2*z
; x = x+1+z;
     lea    R4,$0001   ; R4 = 1
     add    R1,R1,R4   ; x = x+1
     add    R1,R1,R3   ; x = x+z
     store  R1,x[R0]   ; move x to memory
     store  R2,y[R0]   ; move y to memory

Comparison of the styles

Statement by statement.

• Each statement is compiled into a separate block of code.
• Each statement requires loads, computation, then stores.
• A variable may appear in several different registers.
• There may be a lot of redundant loading and storing.
• The object code corresponds straightforwardly to the source code, but it may be unnecessarily long.

Register variable

• The instructions corresponding to the statemnts are mixed together.
• Some statements are executed entirely in the registers.
• A variable is kept in the same register across many statments.
• The use of loads and stores is minimised.
• The object code is concise, but it's harder to see how it corresponds to the source code.
• It's possible to have a mixture of the styles: you don't have to follow one or the other all the time.

Sigma16 also contains some advanced features that use the command line in a shell. These features include text commands for assembling and linking programs, and for running the circuit simulator. These features require some software installation. In addition, building Sigma16 from soure requires some additional software that must be installed. All of the software required is free and open source, and all of it runs on Windows, Macintosh, and Gnu/Linux.

The architecture, software tools, and documentation were designed, implemented, and written by John O'Donnell. Contact email: john.t.odonnell9@gmail.com

Copyright (C) 2020, 2021 John T. O'Donnell

License: GNU GPL Version 3 or later. The full text of the GPL-3 license is given below.

Sigma16 is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. Sigma16 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with Sigma16. If not, see https://www.gnu.org/licenses/.

If you encounter a problem with the app, please file a bug report. It is essential in a bug report (for any software, not just Sigma16) to provide as much as possible of the following information.

• State what version of the software you are running. This is visible in the Welcome page, as well as the User Guide and the Options page.
• State what browser and operating system you are using. There are some incompatibilities between Chrome, Firefox, Edge, and Safari, as well as differences between operating systems.
• Describe what the problem was.
• Provide the source code of the assembly language program you are running.
• If possible, provide some photos or screen shots showing the app at the point where the problem arose. Smartphone photos are fine. Try to show the processor display, including the registers.

GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007

Copyright © 2007 Free Software Foundation, Inc. https://fsf.org/

Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.

Preamble The GNU General Public License is a free, copyleft license for software and other kinds of works.

The licenses for most software and other practical works are designed to take away your freedom to share and change the works. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change all versions of a program–to make sure it remains free software for all its users. We, the Free Software Foundation, use the GNU General Public License for most of our software; it applies also to any other work released this way by its authors. You can apply it to your programs, too.

When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for them if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs, and that you know you can do these things.

To protect your rights, we need to prevent others from denying you these rights or asking you to surrender the rights. Therefore, you have certain responsibilities if you distribute copies of the software, or if you modify it: responsibilities to respect the freedom of others.

For example, if you distribute copies of such a program, whether gratis or for a fee, you must pass on to the recipients the same freedoms that you received. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.

Developers that use the GNU GPL protect your rights with two steps: (1) assert copyright on the software, and (2) offer you this License giving you legal permission to copy, distribute and/or modify it.

For the developers' and authors' protection, the GPL clearly explains that there is no warranty for this free software. For both users' and authors' sake, the GPL requires that modified versions be marked as changed, so that their problems will not be attributed erroneously to authors of previous versions.

Some devices are designed to deny users access to install or run modified versions of the software inside them, although the manufacturer can do so. This is fundamentally incompatible with the aim of protecting users' freedom to change the software. The systematic pattern of such abuse occurs in the area of products for individuals to use, which is precisely where it is most unacceptable. Therefore, we have designed this version of the GPL to prohibit the practice for those products. If such problems arise substantially in other domains, we stand ready to extend this provision to those domains in future versions of the GPL, as needed to protect the freedom of users.

Finally, every program is threatened constantly by software patents. States should not allow patents to restrict development and use of software on general-purpose computers, but in those that do, we wish to avoid the special danger that patents applied to a free program could make it effectively proprietary. To prevent this, the GPL assures that patents cannot be used to render the program non-free.

The precise terms and conditions for copying, distribution and modification follow.

TERMS AND CONDITIONS

1. Definitions.

“This License” refers to version 3 of the GNU General Public License.

“Copyright” also means copyright-like laws that apply to other kinds of works, such as semiconductor masks.

“The Program” refers to any copyrightable work licensed under this License. Each licensee is addressed as “you”. “Licensees” and “recipients” may be individuals or organizations.

To “modify” a work means to copy from or adapt all or part of the work in a fashion requiring copyright permission, other than the making of an exact copy. The resulting work is called a “modified version” of the earlier work or a work “based on” the earlier work.

A “covered work” means either the unmodified Program or a work based on the Program.

To “propagate” a work means to do anything with it that, without permission, would make you directly or secondarily liable for infringement under applicable copyright law, except executing it on a computer or modifying a private copy. Propagation includes copying, distribution (with or without modification), making available to the public, and in some countries other activities as well.

To “convey” a work means any kind of propagation that enables other parties to make or receive copies. Mere interaction with a user through a computer network, with no transfer of a copy, is not conveying.

An interactive user interface displays “Appropriate Legal Notices” to the extent that it includes a convenient and prominently visible feature that (1) displays an appropriate copyright notice, and (2) tells the user that there is no warranty for the work (except to the extent that warranties are provided), that licensees may convey the work under this License, and how to view a copy of this License. If the interface presents a list of user commands or options, such as a menu, a prominent item in the list meets this criterion.

1. Source Code.

The “source code” for a work means the preferred form of the work for making modifications to it. “Object code” means any non-source form of a work.

A “Standard Interface” means an interface that either is an official standard defined by a recognized standards body, or, in the case of interfaces specified for a particular programming language, one that is widely used among developers working in that language.

The “System Libraries” of an executable work include anything, other than the work as a whole, that (a) is included in the normal form of packaging a Major Component, but which is not part of that Major Component, and (b) serves only to enable use of the work with that Major Component, or to implement a Standard Interface for which an implementation is available to the public in source code form. A “Major Component”, in this context, means a major essential component (kernel, window system, and so on) of the specific operating system (if any) on which the executable work runs, or a compiler used to produce the work, or an object code interpreter used to run it.

The “Corresponding Source” for a work in object code form means all the source code needed to generate, install, and (for an executable work) run the object code and to modify the work, including scripts to control those activities. However, it does not include the work's System Libraries, or general-purpose tools or generally available free programs which are used unmodified in performing those activities but which are not part of the work. For example, Corresponding Source includes interface definition files associated with source files for the work, and the source code for shared libraries and dynamically linked subprograms that the work is specifically designed to require, such as by intimate data communication or control flow between those subprograms and other parts of the work.

The Corresponding Source need not include anything that users can regenerate automatically from other parts of the Corresponding Source.

The Corresponding Source for a work in source code form is that same work.

1. Basic Permissions.

All rights granted under this License are granted for the term of copyright on the Program, and are irrevocable provided the stated conditions are met. This License explicitly affirms your unlimited permission to run the unmodified Program. The output from running a covered work is covered by this License only if the output, given its content, constitutes a covered work. This License acknowledges your rights of fair use or other equivalent, as provided by copyright law.

You may make, run and propagate covered works that you do not convey, without conditions so long as your license otherwise remains in force. You may convey covered works to others for the sole purpose of having them make modifications exclusively for you, or provide you with facilities for running those works, provided that you comply with the terms of this License in conveying all material for which you do not control copyright. Those thus making or running the covered works for you must do so exclusively on your behalf, under your direction and control, on terms that prohibit them from making any copies of your copyrighted material outside their relationship with you.

Conveying under any other circumstances is permitted solely under the conditions stated below. Sublicensing is not allowed; section 10 makes it unnecessary.

1. Protecting Users' Legal Rights From Anti-Circumvention Law.

No covered work shall be deemed part of an effective technological measure under any applicable law fulfilling obligations under article 11 of the WIPO copyright treaty adopted on 20 December 1996, or similar laws prohibiting or restricting circumvention of such measures.

When you convey a covered work, you waive any legal power to forbid circumvention of technological measures to the extent such circumvention is effected by exercising rights under this License with respect to the covered work, and you disclaim any intention to limit operation or modification of the work as a means of enforcing, against the work's users, your or third parties' legal rights to forbid circumvention of technological measures.

1. Conveying Verbatim Copies.

You may convey verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice; keep intact all notices stating that this License and any non-permissive terms added in accord with section 7 apply to the code; keep intact all notices of the absence of any warranty; and give all recipients a copy of this License along with the Program.

You may charge any price or no price for each copy that you convey, and you may offer support or warranty protection for a fee.

1. Conveying Modified Source Versions.

You may convey a work based on the Program, or the modifications to produce it from the Program, in the form of source code under the terms of section 4, provided that you also meet all of these conditions:

a) The work must carry prominent notices stating that you modified it, and giving a relevant date. b) The work must carry prominent notices stating that it is released under this License and any conditions added under section 7. This requirement modifies the requirement in section 4 to “keep intact all notices”. c) You must license the entire work, as a whole, under this License to anyone who comes into possession of a copy. This License will therefore apply, along with any applicable section 7 additional terms, to the whole of the work, and all its parts, regardless of how they are packaged. This License gives no permission to license the work in any other way, but it does not invalidate such permission if you have separately received it. d) If the work has interactive user interfaces, each must display Appropriate Legal Notices; however, if the Program has interactive interfaces that do not display Appropriate Legal Notices, your work need not make them do so. A compilation of a covered work with other separate and independent works, which are not by their nature extensions of the covered work, and which are not combined with it such as to form a larger program, in or on a volume of a storage or distribution medium, is called an “aggregate” if the compilation and its resulting copyright are not used to limit the access or legal rights of the compilation's users beyond what the individual works permit. Inclusion of a covered work in an aggregate does not cause this License to apply to the other parts of the aggregate.

1. Conveying Non-Source Forms.

You may convey a covered work in object code form under the terms of sections 4 and 5, provided that you also convey the machine-readable Corresponding Source under the terms of this License, in one of these ways:

a) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by the Corresponding Source fixed on a durable physical medium customarily used for software interchange. b) Convey the object code in, or embodied in, a physical product (including a physical distribution medium), accompanied by a written offer, valid for at least three years and valid for as long as you offer spare parts or customer support for that product model, to give anyone who possesses the object code either (1) a copy of the Corresponding Source for all the software in the product that is covered by this License, on a durable physical medium customarily used for software interchange, for a price no more than your reasonable cost of physically performing this conveying of source, or (2) access to copy the Corresponding Source from a network server at no charge. c) Convey individual copies of the object code with a copy of the written offer to provide the Corresponding Source. This alternative is allowed only occasionally and noncommercially, and only if you received the object code with such an offer, in accord with subsection 6b. d) Convey the object code by offering access from a designated place (gratis or for a charge), and offer equivalent access to the Corresponding Source in the same way through the same place at no further charge. You need not require recipients to copy the Corresponding Source along with the object code. If the place to copy the object code is a network server, the Corresponding Source may be on a different server (operated by you or a third party) that supports equivalent copying facilities, provided you maintain clear directions next to the object code saying where to find the Corresponding Source. Regardless of what server hosts the Corresponding Source, you remain obligated to ensure that it is available for as long as needed to satisfy these requirements. e) Convey the object code using peer-to-peer transmission, provided you inform other peers where the object code and Corresponding Source of the work are being offered to the general public at no charge under subsection 6d. A separable portion of the object code, whose source code is excluded from the Corresponding Source as a System Library, need not be included in conveying the object code work.

A “User Product” is either (1) a “consumer product”, which means any tangible personal property which is normally used for personal, family, or household purposes, or (2) anything designed or sold for incorporation into a dwelling. In determining whether a product is a consumer product, doubtful cases shall be resolved in favor of coverage. For a particular product received by a particular user, “normally used” refers to a typical or common use of that class of product, regardless of the status of the particular user or of the way in which the particular user actually uses, or expects or is expected to use, the product. A product is a consumer product regardless of whether the product has substantial commercial, industrial or non-consumer uses, unless such uses represent the only significant mode of use of the product.

“Installation Information” for a User Product means any methods, procedures, authorization keys, or other information required to install and execute modified versions of a covered work in that User Product from a modified version of its Corresponding Source. The information must suffice to ensure that the continued functioning of the modified object code is in no case prevented or interfered with solely because modification has been made.

If you convey an object code work under this section in, or with, or specifically for use in, a User Product, and the conveying occurs as part of a transaction in which the right of possession and use of the User Product is transferred to the recipient in perpetuity or for a fixed term (regardless of how the transaction is characterized), the Corresponding Source conveyed under this section must be accompanied by the Installation Information. But this requirement does not apply if neither you nor any third party retains the ability to install modified object code on the User Product (for example, the work has been installed in ROM).

The requirement to provide Installation Information does not include a requirement to continue to provide support service, warranty, or updates for a work that has been modified or installed by the recipient, or for the User Product in which it has been modified or installed. Access to a network may be denied when the modification itself materially and adversely affects the operation of the network or violates the rules and protocols for communication across the network.

Corresponding Source conveyed, and Installation Information provided, in accord with this section must be in a format that is publicly documented (and with an implementation available to the public in source code form), and must require no special password or key for unpacking, reading or copying.

1. Additional Terms.

“Additional permissions” are terms that supplement the terms of this License by making exceptions from one or more of its conditions. Additional permissions that are applicable to the entire Program shall be treated as though they were included in this License, to the extent that they are valid under applicable law. If additional permissions apply only to part of the Program, that part may be used separately under those permissions, but the entire Program remains governed by this License without regard to the additional permissions.

When you convey a copy of a covered work, you may at your option remove any additional permissions from that copy, or from any part of it. (Additional permissions may be written to require their own removal in certain cases when you modify the work.) You may place additional permissions on material, added by you to a covered work, for which you have or can give appropriate copyright permission.

Notwithstanding any other provision of this License, for material you add to a covered work, you may (if authorized by the copyright holders of that material) supplement the terms of this License with terms:

a) Disclaiming warranty or limiting liability differently from the terms of sections 15 and 16 of this License; or b) Requiring preservation of specified reasonable legal notices or author attributions in that material or in the Appropriate Legal Notices displayed by works containing it; or c) Prohibiting misrepresentation of the origin of that material, or requiring that modified versions of such material be marked in reasonable ways as different from the original version; or d) Limiting the use for publicity purposes of names of licensors or authors of the material; or e) Declining to grant rights under trademark law for use of some trade names, trademarks, or service marks; or f) Requiring indemnification of licensors and authors of that material by anyone who conveys the material (or modified versions of it) with contractual assumptions of liability to the recipient, for any liability that these contractual assumptions directly impose on those licensors and authors. All other non-permissive additional terms are considered “further restrictions” within the meaning of section 10. If the Program as you received it, or any part of it, contains a notice stating that it is governed by this License along with a term that is a further restriction, you may remove that term. If a license document contains a further restriction but permits relicensing or conveying under this License, you may add to a covered work material governed by the terms of that license document, provided that the further restriction does not survive such relicensing or conveying.

If you add terms to a covered work in accord with this section, you must place, in the relevant source files, a statement of the additional terms that apply to those files, or a notice indicating where to find the applicable terms.

Additional terms, permissive or non-permissive, may be stated in the form of a separately written license, or stated as exceptions; the above requirements apply either way.

1. Termination.

You may not propagate or modify a covered work except as expressly provided under this License. Any attempt otherwise to propagate or modify it is void, and will automatically terminate your rights under this License (including any patent licenses granted under the third paragraph of section 11).

However, if you cease all violation of this License, then your license from a particular copyright holder is reinstated (a) provisionally, unless and until the copyright holder explicitly and finally terminates your license, and (b) permanently, if the copyright holder fails to notify you of the violation by some reasonable means prior to 60 days after the cessation.

Moreover, your license from a particular copyright holder is reinstated permanently if the copyright holder notifies you of the violation by some reasonable means, this is the first time you have received notice of violation of this License (for any work) from that copyright holder, and you cure the violation prior to 30 days after your receipt of the notice.

Termination of your rights under this section does not terminate the licenses of parties who have received copies or rights from you under this License. If your rights have been terminated and not permanently reinstated, you do not qualify to receive new licenses for the same material under section 10.

1. Acceptance Not Required for Having Copies.

You are not required to accept this License in order to receive or run a copy of the Program. Ancillary propagation of a covered work occurring solely as a consequence of using peer-to-peer transmission to receive a copy likewise does not require acceptance. However, nothing other than this License grants you permission to propagate or modify any covered work. These actions infringe copyright if you do not accept this License. Therefore, by modifying or propagating a covered work, you indicate your acceptance of this License to do so.

1. Automatic Licensing of Downstream Recipients.

Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and propagate that work, subject to this License. You are not responsible for enforcing compliance by third parties with this License.

An “entity transaction” is a transaction transferring control of an organization, or substantially all assets of one, or subdividing an organization, or merging organizations. If propagation of a covered work results from an entity transaction, each party to that transaction who receives a copy of the work also receives whatever licenses to the work the party's predecessor in interest had or could give under the previous paragraph, plus a right to possession of the Corresponding Source of the work from the predecessor in interest, if the predecessor has it or can get it with reasonable efforts.

You may not impose any further restrictions on the exercise of the rights granted or affirmed under this License. For example, you may not impose a license fee, royalty, or other charge for exercise of rights granted under this License, and you may not initiate litigation (including a cross-claim or counterclaim in a lawsuit) alleging that any patent claim is infringed by making, using, selling, offering for sale, or importing the Program or any portion of it.

1. Patents.

A “contributor” is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. The work thus licensed is called the contributor's “contributor version”.

A contributor's “essential patent claims” are all patent claims owned or controlled by the contributor, whether already acquired or hereafter acquired, that would be infringed by some manner, permitted by this License, of making, using, or selling its contributor version, but do not include claims that would be infringed only as a consequence of further modification of the contributor version. For purposes of this definition, “control” includes the right to grant patent sublicenses in a manner consistent with the requirements of this License.

Each contributor grants you a non-exclusive, worldwide, royalty-free patent license under the contributor's essential patent claims, to make, use, sell, offer for sale, import and otherwise run, modify and propagate the contents of its contributor version.

In the following three paragraphs, a “patent license” is any express agreement or commitment, however denominated, not to enforce a patent (such as an express permission to practice a patent or covenant not to sue for patent infringement). To “grant” such a patent license to a party means to make such an agreement or commitment not to enforce a patent against the party.

If you convey a covered work, knowingly relying on a patent license, and the Corresponding Source of the work is not available for anyone to copy, free of charge and under the terms of this License, through a publicly available network server or other readily accessible means, then you must either (1) cause the Corresponding Source to be so available, or (2) arrange to deprive yourself of the benefit of the patent license for this particular work, or (3) arrange, in a manner consistent with the requirements of this License, to extend the patent license to downstream recipients. “Knowingly relying” means you have actual knowledge that, but for the patent license, your conveying the covered work in a country, or your recipient's use of the covered work in a country, would infringe one or more identifiable patents in that country that you have reason to believe are valid.

If, pursuant to or in connection with a single transaction or arrangement, you convey, or propagate by procuring conveyance of, a covered work, and grant a patent license to some of the parties receiving the covered work authorizing them to use, propagate, modify or convey a specific copy of the covered work, then the patent license you grant is automatically extended to all recipients of the covered work and works based on it.

A patent license is “discriminatory” if it does not include within the scope of its coverage, prohibits the exercise of, or is conditioned on the non-exercise of one or more of the rights that are specifically granted under this License. You may not convey a covered work if you are a party to an arrangement with a third party that is in the business of distributing software, under which you make payment to the third party based on the extent of your activity of conveying the work, and under which the third party grants, to any of the parties who would receive the covered work from you, a discriminatory patent license (a) in connection with copies of the covered work conveyed by you (or copies made from those copies), or (b) primarily for and in connection with specific products or compilations that contain the covered work, unless you entered into that arrangement, or that patent license was granted, prior to 28 March 2007.

Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law.

1. No Surrender of Others' Freedom.

If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program.

1. Use with the GNU Affero General Public License.

Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such.

1. Revised Versions of this License.

The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.

Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License “or any later version” applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation.

If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program.

Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version.

1. Disclaimer of Warranty.

THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.

1. Limitation of Liability.

IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

1. Interpretation of Sections 15 and 16.

If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee.

END OF TERMS AND CONDITIONS

How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.

To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found.

<one line to give the program's name and a brief idea of what it does.> Copyright (C) <year> <name of author>

This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program. If not, see https://www.gnu.org/licenses/. Also add information on how to contact you by electronic and paper mail.

If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode:

<program> Copyright (C) <year> <name of author> This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for Details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”.

You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see https://www.gnu.org/licenses/.

The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read https://www.gnu.org/licenses/why-not-lgpl.html.

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